mirror of
https://github.com/AsahiLinux/u-boot
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acbb871af5
Adds support for both DSI outputs found on Tegra. Only very minimal functionality is implemented, so advanced features like ganged mode won't work. Driver is heavily based on mainline Tegra DSI and re-uses much of its features. Only T30 is supported for now but T20 support can be added if any supported devices will be found. Driver is wrapped as panel driver since Tegra DC driver supports only panel drivers calls. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
864 lines
22 KiB
C
864 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013 NVIDIA Corporation
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* Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <misc.h>
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#include <mipi_display.h>
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#include <mipi_dsi.h>
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#include <backlight.h>
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#include <panel.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <power/regulator.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/display.h>
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#include <asm/arch-tegra30/dsi.h>
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#include "mipi-phy.h"
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#define USEC_PER_SEC 1000000L
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#define NSEC_PER_SEC 1000000000L
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struct tegra_dsi_priv {
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struct mipi_dsi_host host;
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struct mipi_dsi_device device;
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struct mipi_dphy_timing dphy_timing;
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struct udevice *panel;
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struct display_timing timing;
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struct dsi_ctlr *dsi;
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struct udevice *avdd;
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enum tegra_dsi_format format;
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int dsi_clk;
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int video_fifo_depth;
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int host_fifo_depth;
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};
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static void tegra_dc_enable_controller(struct udevice *dev)
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{
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struct tegra_dc_plat *dc_plat = dev_get_plat(dev);
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struct dc_ctlr *dc = dc_plat->dc;
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u32 value;
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value = readl(&dc->disp.disp_win_opt);
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value |= DSI_ENABLE;
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writel(value, &dc->disp.disp_win_opt);
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writel(GENERAL_UPDATE, &dc->cmd.state_ctrl);
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writel(GENERAL_ACT_REQ, &dc->cmd.state_ctrl);
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}
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static const char * const error_report[16] = {
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"SoT Error",
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"SoT Sync Error",
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"EoT Sync Error",
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"Escape Mode Entry Command Error",
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"Low-Power Transmit Sync Error",
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"Peripheral Timeout Error",
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"False Control Error",
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"Contention Detected",
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"ECC Error, single-bit",
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"ECC Error, multi-bit",
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"Checksum Error",
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"DSI Data Type Not Recognized",
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"DSI VC ID Invalid",
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"Invalid Transmission Length",
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"Reserved",
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"DSI Protocol Violation",
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};
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static ssize_t tegra_dsi_read_response(struct dsi_misc_reg *misc,
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const struct mipi_dsi_msg *msg,
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size_t count)
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{
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u8 *rx = msg->rx_buf;
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unsigned int i, j, k;
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size_t size = 0;
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u16 errors;
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u32 value;
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/* read and parse packet header */
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value = readl(&misc->dsi_rd_data);
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switch (value & 0x3f) {
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case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
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errors = (value >> 8) & 0xffff;
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printf("%s: Acknowledge and error report: %04x\n",
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__func__, errors);
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for (i = 0; i < ARRAY_SIZE(error_report); i++)
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if (errors & BIT(i))
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printf("%s: %2u: %s\n", __func__, i,
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error_report[i]);
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break;
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case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
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rx[0] = (value >> 8) & 0xff;
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size = 1;
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break;
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case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
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rx[0] = (value >> 8) & 0xff;
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rx[1] = (value >> 16) & 0xff;
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size = 2;
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break;
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case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
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size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
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break;
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case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
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size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
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break;
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default:
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printf("%s: unhandled response type: %02x\n",
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__func__, value & 0x3f);
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return -EPROTO;
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}
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size = min(size, msg->rx_len);
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if (msg->rx_buf && size > 0) {
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for (i = 0, j = 0; i < count - 1; i++, j += 4) {
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u8 *rx = msg->rx_buf + j;
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value = readl(&misc->dsi_rd_data);
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for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
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rx[j + k] = (value >> (k << 3)) & 0xff;
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}
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}
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return size;
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}
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static int tegra_dsi_transmit(struct dsi_misc_reg *misc,
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unsigned long timeout)
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{
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writel(DSI_TRIGGER_HOST, &misc->dsi_trigger);
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while (timeout--) {
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u32 value = readl(&misc->dsi_trigger);
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if ((value & DSI_TRIGGER_HOST) == 0)
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return 0;
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udelay(1000);
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}
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debug("timeout waiting for transmission to complete\n");
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return -ETIMEDOUT;
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}
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static int tegra_dsi_wait_for_response(struct dsi_misc_reg *misc,
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unsigned long timeout)
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{
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while (timeout--) {
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u32 value = readl(&misc->dsi_status);
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u8 count = value & 0x1f;
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if (count > 0)
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return count;
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udelay(1000);
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}
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debug("peripheral returned no data\n");
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return -ETIMEDOUT;
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}
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static void tegra_dsi_writesl(struct dsi_misc_reg *misc,
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const void *buffer, size_t size)
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{
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const u8 *buf = buffer;
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size_t i, j;
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u32 value;
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for (j = 0; j < size; j += 4) {
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value = 0;
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for (i = 0; i < 4 && j + i < size; i++)
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value |= buf[j + i] << (i << 3);
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writel(value, &misc->dsi_wr_data);
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}
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}
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static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
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const struct mipi_dsi_msg *msg)
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{
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struct udevice *dev = (struct udevice *)host->dev;
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struct tegra_dsi_priv *priv = dev_get_priv(dev);
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struct dsi_misc_reg *misc = &priv->dsi->misc;
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struct mipi_dsi_packet packet;
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const u8 *header;
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size_t count;
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ssize_t err;
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u32 value;
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err = mipi_dsi_create_packet(&packet, msg);
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if (err < 0)
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return err;
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header = packet.header;
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/* maximum FIFO depth is 1920 words */
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if (packet.size > priv->video_fifo_depth * 4)
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return -ENOSPC;
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/* reset underflow/overflow flags */
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value = readl(&misc->dsi_status);
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if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
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value = DSI_HOST_CONTROL_FIFO_RESET;
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writel(value, &misc->host_dsi_ctrl);
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udelay(10);
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}
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value = readl(&misc->dsi_pwr_ctrl);
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value |= DSI_POWER_CONTROL_ENABLE;
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writel(value, &misc->dsi_pwr_ctrl);
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mdelay(5);
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value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
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DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
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/*
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* The host FIFO has a maximum of 64 words, so larger transmissions
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* need to use the video FIFO.
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*/
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if (packet.size > priv->host_fifo_depth * 4)
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value |= DSI_HOST_CONTROL_FIFO_SEL;
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writel(value, &misc->host_dsi_ctrl);
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/*
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* For reads and messages with explicitly requested ACK, generate a
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* BTA sequence after the transmission of the packet.
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*/
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if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
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(msg->rx_buf && msg->rx_len > 0)) {
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value = readl(&misc->host_dsi_ctrl);
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value |= DSI_HOST_CONTROL_PKT_BTA;
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writel(value, &misc->host_dsi_ctrl);
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}
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value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
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writel(value, &misc->dsi_ctrl);
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/* write packet header, ECC is generated by hardware */
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value = header[2] << 16 | header[1] << 8 | header[0];
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writel(value, &misc->dsi_wr_data);
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/* write payload (if any) */
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if (packet.payload_length > 0)
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tegra_dsi_writesl(misc, packet.payload,
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packet.payload_length);
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err = tegra_dsi_transmit(misc, 250);
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if (err < 0)
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return err;
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if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
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(msg->rx_buf && msg->rx_len > 0)) {
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err = tegra_dsi_wait_for_response(misc, 250);
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if (err < 0)
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return err;
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count = err;
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value = readl(&misc->dsi_rd_data);
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switch (value) {
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case 0x84:
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debug("%s: ACK\n", __func__);
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break;
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case 0x87:
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debug("%s: ESCAPE\n", __func__);
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break;
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default:
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printf("%s: unknown status: %08x\n", __func__, value);
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break;
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}
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if (count > 1) {
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err = tegra_dsi_read_response(misc, msg, count);
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if (err < 0) {
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printf("%s: failed to parse response: %zd\n",
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__func__, err);
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} else {
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/*
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* For read commands, return the number of
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* bytes returned by the peripheral.
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*/
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count = err;
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}
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}
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} else {
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/*
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* For write commands, we have transmitted the 4-byte header
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* plus the variable-length payload.
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*/
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count = 4 + packet.payload_length;
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}
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return count;
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}
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struct mipi_dsi_host_ops tegra_dsi_bridge_host_ops = {
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.transfer = tegra_dsi_host_transfer,
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};
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#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
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#define PKT_LEN0(len) (((len) & 0x07) << 0)
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#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
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#define PKT_LEN1(len) (((len) & 0x07) << 10)
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#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
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#define PKT_LEN2(len) (((len) & 0x07) << 20)
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#define PKT_LP BIT(30)
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#define NUM_PKT_SEQ 12
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/*
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* non-burst mode with sync pulses
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*/
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static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
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[ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
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PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
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PKT_LP,
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[ 1] = 0,
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[ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
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PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
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PKT_LP,
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[ 3] = 0,
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[ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
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PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
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PKT_LP,
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[ 5] = 0,
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[ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
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PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
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[ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
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PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
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PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
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[ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
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PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
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PKT_LP,
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[ 9] = 0,
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[10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
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PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
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[11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
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PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
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PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
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};
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/*
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* non-burst mode with sync events
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*/
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static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
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[ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
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PKT_LP,
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[ 1] = 0,
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[ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
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PKT_LP,
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[ 3] = 0,
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[ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
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PKT_LP,
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[ 5] = 0,
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[ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
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PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
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[ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
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[ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
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PKT_LP,
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[ 9] = 0,
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[10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
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PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
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[11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
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};
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static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
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[ 0] = 0,
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[ 1] = 0,
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[ 2] = 0,
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[ 3] = 0,
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[ 4] = 0,
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[ 5] = 0,
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[ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
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[ 7] = 0,
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[ 8] = 0,
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[ 9] = 0,
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[10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
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[11] = 0,
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};
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static void tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
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unsigned int *mulp, unsigned int *divp)
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{
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switch (format) {
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case MIPI_DSI_FMT_RGB666_PACKED:
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case MIPI_DSI_FMT_RGB888:
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*mulp = 3;
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*divp = 1;
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break;
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case MIPI_DSI_FMT_RGB565:
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*mulp = 2;
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*divp = 1;
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break;
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case MIPI_DSI_FMT_RGB666:
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*mulp = 9;
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*divp = 4;
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break;
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default:
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break;
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}
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}
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static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
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enum tegra_dsi_format *fmt)
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{
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switch (format) {
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case MIPI_DSI_FMT_RGB888:
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*fmt = TEGRA_DSI_FORMAT_24P;
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break;
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|
|
case MIPI_DSI_FMT_RGB666:
|
|
*fmt = TEGRA_DSI_FORMAT_18NP;
|
|
break;
|
|
|
|
case MIPI_DSI_FMT_RGB666_PACKED:
|
|
*fmt = TEGRA_DSI_FORMAT_18P;
|
|
break;
|
|
|
|
case MIPI_DSI_FMT_RGB565:
|
|
*fmt = TEGRA_DSI_FORMAT_16P;
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_dsi_pad_calibrate(struct dsi_pad_ctrl_reg *pad)
|
|
{
|
|
u32 value;
|
|
|
|
/* start calibration */
|
|
value = DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
|
|
DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
|
|
DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
|
|
DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
|
|
DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6) |
|
|
DSI_PAD_CONTROL_PAD_PDIO(0) |
|
|
DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
|
|
DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0);
|
|
writel(value, &pad->pad_ctrl);
|
|
|
|
clock_enable(PERIPH_ID_VI);
|
|
clock_enable(PERIPH_ID_CSI);
|
|
udelay(2);
|
|
reset_set_enable(PERIPH_ID_VI, 0);
|
|
reset_set_enable(PERIPH_ID_CSI, 0);
|
|
|
|
value = MIPI_CAL_TERMOSA(0x4);
|
|
writel(value, TEGRA_VI_BASE + (CSI_CILA_MIPI_CAL_CONFIG_0 << 2));
|
|
|
|
value = MIPI_CAL_TERMOSB(0x4);
|
|
writel(value, TEGRA_VI_BASE + (CSI_CILB_MIPI_CAL_CONFIG_0 << 2));
|
|
|
|
value = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
|
|
writel(value, TEGRA_VI_BASE + (CSI_DSI_MIPI_CAL_CONFIG << 2));
|
|
|
|
value = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
|
|
writel(value, TEGRA_VI_BASE + (CSI_MIPIBIAS_PAD_CONFIG << 2));
|
|
|
|
value = PAD_CIL_PDVREG(0x0);
|
|
writel(value, TEGRA_VI_BASE + (CSI_CIL_PAD_CONFIG << 2));
|
|
}
|
|
|
|
static void tegra_dsi_set_timeout(struct dsi_timeout_reg *rtimeout,
|
|
unsigned long bclk,
|
|
unsigned int vrefresh)
|
|
{
|
|
unsigned int timeout;
|
|
u32 value;
|
|
|
|
/* one frame high-speed transmission timeout */
|
|
timeout = (bclk / vrefresh) / 512;
|
|
value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
|
|
writel(value, &rtimeout->dsi_timeout_0);
|
|
|
|
/* 2 ms peripheral timeout for panel */
|
|
timeout = 2 * bclk / 512 * 1000;
|
|
value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
|
|
writel(value, &rtimeout->dsi_timeout_1);
|
|
|
|
value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
|
|
writel(value, &rtimeout->dsi_to_tally);
|
|
}
|
|
|
|
static void tegra_dsi_set_phy_timing(struct dsi_timing_reg *ptiming,
|
|
unsigned long period,
|
|
const struct mipi_dphy_timing *dphy_timing)
|
|
{
|
|
u32 value;
|
|
|
|
value = DSI_TIMING_FIELD(dphy_timing->hsexit, period, 1) << 24 |
|
|
DSI_TIMING_FIELD(dphy_timing->hstrail, period, 0) << 16 |
|
|
DSI_TIMING_FIELD(dphy_timing->hszero, period, 3) << 8 |
|
|
DSI_TIMING_FIELD(dphy_timing->hsprepare, period, 1);
|
|
writel(value, &ptiming->dsi_phy_timing_0);
|
|
|
|
value = DSI_TIMING_FIELD(dphy_timing->clktrail, period, 1) << 24 |
|
|
DSI_TIMING_FIELD(dphy_timing->clkpost, period, 1) << 16 |
|
|
DSI_TIMING_FIELD(dphy_timing->clkzero, period, 1) << 8 |
|
|
DSI_TIMING_FIELD(dphy_timing->lpx, period, 1);
|
|
writel(value, &ptiming->dsi_phy_timing_1);
|
|
|
|
value = DSI_TIMING_FIELD(dphy_timing->clkprepare, period, 1) << 16 |
|
|
DSI_TIMING_FIELD(dphy_timing->clkpre, period, 1) << 8 |
|
|
DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
|
|
writel(value, &ptiming->dsi_phy_timing_2);
|
|
|
|
value = DSI_TIMING_FIELD(dphy_timing->taget, period, 1) << 16 |
|
|
DSI_TIMING_FIELD(dphy_timing->tasure, period, 1) << 8 |
|
|
DSI_TIMING_FIELD(dphy_timing->tago, period, 1);
|
|
writel(value, &ptiming->dsi_bta_timing);
|
|
}
|
|
|
|
static void tegra_dsi_configure(struct udevice *dev,
|
|
unsigned long mode_flags)
|
|
{
|
|
struct tegra_dsi_priv *priv = dev_get_priv(dev);
|
|
struct mipi_dsi_device *device = &priv->device;
|
|
struct display_timing *timing = &priv->timing;
|
|
|
|
struct dsi_misc_reg *misc = &priv->dsi->misc;
|
|
struct dsi_pkt_seq_reg *pkt = &priv->dsi->pkt;
|
|
struct dsi_pkt_len_reg *len = &priv->dsi->len;
|
|
|
|
unsigned int hact, hsw, hbp, hfp, i, mul, div;
|
|
const u32 *pkt_seq;
|
|
u32 value;
|
|
|
|
tegra_dsi_get_muldiv(device->format, &mul, &div);
|
|
|
|
if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
|
|
printf("[DSI] Non-burst video mode with sync pulses\n");
|
|
pkt_seq = pkt_seq_video_non_burst_sync_pulses;
|
|
} else if (mode_flags & MIPI_DSI_MODE_VIDEO) {
|
|
printf("[DSI] Non-burst video mode with sync events\n");
|
|
pkt_seq = pkt_seq_video_non_burst_sync_events;
|
|
} else {
|
|
printf("[DSI] Command mode\n");
|
|
pkt_seq = pkt_seq_command_mode;
|
|
}
|
|
|
|
value = DSI_CONTROL_CHANNEL(0) |
|
|
DSI_CONTROL_FORMAT(priv->format) |
|
|
DSI_CONTROL_LANES(device->lanes - 1) |
|
|
DSI_CONTROL_SOURCE(0);
|
|
writel(value, &misc->dsi_ctrl);
|
|
|
|
writel(priv->video_fifo_depth, &misc->dsi_max_threshold);
|
|
|
|
value = DSI_HOST_CONTROL_HS;
|
|
writel(value, &misc->host_dsi_ctrl);
|
|
|
|
value = readl(&misc->dsi_ctrl);
|
|
|
|
if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
|
|
value |= DSI_CONTROL_HS_CLK_CTRL;
|
|
|
|
value &= ~DSI_CONTROL_TX_TRIG(3);
|
|
|
|
/* enable DCS commands for command mode */
|
|
if (mode_flags & MIPI_DSI_MODE_VIDEO)
|
|
value &= ~DSI_CONTROL_DCS_ENABLE;
|
|
else
|
|
value |= DSI_CONTROL_DCS_ENABLE;
|
|
|
|
value |= DSI_CONTROL_VIDEO_ENABLE;
|
|
value &= ~DSI_CONTROL_HOST_ENABLE;
|
|
writel(value, &misc->dsi_ctrl);
|
|
|
|
for (i = 0; i < NUM_PKT_SEQ; i++)
|
|
writel(pkt_seq[i], &pkt->dsi_pkt_seq_0_lo + i);
|
|
|
|
if (mode_flags & MIPI_DSI_MODE_VIDEO) {
|
|
/* horizontal active pixels */
|
|
hact = timing->hactive.typ * mul / div;
|
|
|
|
/* horizontal sync width */
|
|
hsw = timing->hsync_len.typ * mul / div;
|
|
|
|
/* horizontal back porch */
|
|
hbp = timing->hback_porch.typ * mul / div;
|
|
|
|
if ((mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
|
|
hbp += hsw;
|
|
|
|
/* horizontal front porch */
|
|
hfp = timing->hfront_porch.typ * mul / div;
|
|
|
|
/* subtract packet overhead */
|
|
hsw -= 10;
|
|
hbp -= 14;
|
|
hfp -= 8;
|
|
|
|
writel(hsw << 16 | 0, &len->dsi_pkt_len_0_1);
|
|
writel(hact << 16 | hbp, &len->dsi_pkt_len_2_3);
|
|
writel(hfp, &len->dsi_pkt_len_4_5);
|
|
writel(0x0f0f << 16, &len->dsi_pkt_len_6_7);
|
|
} else {
|
|
/* 1 byte (DCS command) + pixel data */
|
|
value = 1 + timing->hactive.typ * mul / div;
|
|
|
|
writel(0, &len->dsi_pkt_len_0_1);
|
|
writel(value << 16, &len->dsi_pkt_len_2_3);
|
|
writel(value << 16, &len->dsi_pkt_len_4_5);
|
|
writel(0, &len->dsi_pkt_len_6_7);
|
|
|
|
value = MIPI_DCS_WRITE_MEMORY_START << 8 |
|
|
MIPI_DCS_WRITE_MEMORY_CONTINUE;
|
|
writel(value, &len->dsi_dcs_cmds);
|
|
}
|
|
|
|
/* set SOL delay (for non-burst mode only) */
|
|
writel(8 * mul / div, &misc->dsi_sol_delay);
|
|
}
|
|
|
|
static int tegra_dsi_encoder_enable(struct udevice *dev)
|
|
{
|
|
struct tegra_dsi_priv *priv = dev_get_priv(dev);
|
|
struct mipi_dsi_device *device = &priv->device;
|
|
struct display_timing *timing = &priv->timing;
|
|
struct dsi_misc_reg *misc = &priv->dsi->misc;
|
|
unsigned int mul, div;
|
|
unsigned long bclk, plld, period;
|
|
u32 value;
|
|
int ret;
|
|
|
|
/* Disable interrupt */
|
|
writel(0, &misc->int_enable);
|
|
|
|
tegra_dsi_pad_calibrate(&priv->dsi->pad);
|
|
|
|
tegra_dsi_get_muldiv(device->format, &mul, &div);
|
|
|
|
/* compute byte clock */
|
|
bclk = (timing->pixelclock.typ * mul) / (div * device->lanes);
|
|
|
|
tegra_dsi_set_timeout(&priv->dsi->timeout, bclk, 60);
|
|
|
|
/*
|
|
* Compute bit clock and round up to the next MHz.
|
|
*/
|
|
plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
|
|
period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
|
|
|
|
ret = mipi_dphy_timing_get_default(&priv->dphy_timing, period);
|
|
if (ret < 0) {
|
|
printf("%s: failed to get D-PHY timing: %d\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = mipi_dphy_timing_validate(&priv->dphy_timing, period);
|
|
if (ret < 0) {
|
|
printf("%s: failed to validate D-PHY timing: %d\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* The D-PHY timing fields are expressed in byte-clock cycles, so
|
|
* multiply the period by 8.
|
|
*/
|
|
tegra_dsi_set_phy_timing(&priv->dsi->ptiming,
|
|
period * 8, &priv->dphy_timing);
|
|
|
|
/* Perform panel HW setup */
|
|
ret = panel_enable_backlight(priv->panel);
|
|
if (ret)
|
|
return ret;
|
|
|
|
tegra_dsi_configure(dev, 0);
|
|
|
|
ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
|
|
if (ret)
|
|
return ret;
|
|
|
|
tegra_dsi_configure(dev, device->mode_flags);
|
|
|
|
tegra_dc_enable_controller(dev);
|
|
|
|
/* enable DSI controller */
|
|
value = readl(&misc->dsi_pwr_ctrl);
|
|
value |= DSI_POWER_CONTROL_ENABLE;
|
|
writel(value, &misc->dsi_pwr_ctrl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_dsi_bridge_set_panel(struct udevice *dev, int percent)
|
|
{
|
|
/* Is not used in tegra dc */
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_dsi_panel_timings(struct udevice *dev,
|
|
struct display_timing *timing)
|
|
{
|
|
struct tegra_dsi_priv *priv = dev_get_priv(dev);
|
|
|
|
memcpy(timing, &priv->timing, sizeof(*timing));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_dsi_init_clocks(struct udevice *dev)
|
|
{
|
|
struct tegra_dsi_priv *priv = dev_get_priv(dev);
|
|
struct mipi_dsi_device *device = &priv->device;
|
|
unsigned int mul, div;
|
|
unsigned long bclk, plld;
|
|
|
|
tegra_dsi_get_muldiv(device->format, &mul, &div);
|
|
|
|
bclk = (priv->timing.pixelclock.typ * mul) /
|
|
(div * device->lanes);
|
|
|
|
plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC);
|
|
|
|
switch (clock_get_osc_freq()) {
|
|
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
|
|
case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
|
|
clock_set_rate(CLOCK_ID_DISPLAY, plld, 12, 0, 8);
|
|
break;
|
|
|
|
case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
|
|
clock_set_rate(CLOCK_ID_DISPLAY, plld, 26, 0, 8);
|
|
break;
|
|
|
|
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
|
|
case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
|
|
clock_set_rate(CLOCK_ID_DISPLAY, plld, 13, 0, 8);
|
|
break;
|
|
|
|
case CLOCK_OSC_FREQ_19_2:
|
|
case CLOCK_OSC_FREQ_38_4:
|
|
default:
|
|
/*
|
|
* These are not supported.
|
|
*/
|
|
break;
|
|
}
|
|
|
|
priv->dsi_clk = clock_decode_periph_id(dev);
|
|
|
|
clock_enable(priv->dsi_clk);
|
|
udelay(2);
|
|
reset_set_enable(priv->dsi_clk, 0);
|
|
}
|
|
|
|
static int tegra_dsi_bridge_probe(struct udevice *dev)
|
|
{
|
|
struct tegra_dsi_priv *priv = dev_get_priv(dev);
|
|
struct mipi_dsi_device *device = &priv->device;
|
|
struct mipi_dsi_panel_plat *mipi_plat;
|
|
int ret;
|
|
|
|
priv->dsi = (struct dsi_ctlr *)dev_read_addr_ptr(dev);
|
|
if (!priv->dsi) {
|
|
printf("%s: No display controller address\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->video_fifo_depth = 480;
|
|
priv->host_fifo_depth = 64;
|
|
|
|
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
|
|
"avdd-dsi-csi-supply", &priv->avdd);
|
|
if (ret)
|
|
debug("%s: Cannot get avdd-dsi-csi-supply: error %d\n",
|
|
__func__, ret);
|
|
|
|
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
|
|
"panel", &priv->panel);
|
|
if (ret) {
|
|
printf("%s: Cannot get panel: error %d\n", __func__, ret);
|
|
return log_ret(ret);
|
|
}
|
|
|
|
panel_get_display_timing(priv->panel, &priv->timing);
|
|
|
|
mipi_plat = dev_get_plat(priv->panel);
|
|
mipi_plat->device = device;
|
|
|
|
priv->host.dev = (struct device *)dev;
|
|
priv->host.ops = &tegra_dsi_bridge_host_ops;
|
|
|
|
device->host = &priv->host;
|
|
device->lanes = mipi_plat->lanes;
|
|
device->format = mipi_plat->format;
|
|
device->mode_flags = mipi_plat->mode_flags;
|
|
|
|
tegra_dsi_get_format(device->format, &priv->format);
|
|
|
|
if (priv->avdd) {
|
|
ret = regulator_set_enable(priv->avdd, true);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
tegra_dsi_init_clocks(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct panel_ops tegra_dsi_bridge_ops = {
|
|
.enable_backlight = tegra_dsi_encoder_enable,
|
|
.set_backlight = tegra_dsi_bridge_set_panel,
|
|
.get_display_timing = tegra_dsi_panel_timings,
|
|
};
|
|
|
|
static const struct udevice_id tegra_dsi_bridge_ids[] = {
|
|
{ .compatible = "nvidia,tegra30-dsi" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(tegra_dsi) = {
|
|
.name = "tegra_dsi",
|
|
.id = UCLASS_PANEL,
|
|
.of_match = tegra_dsi_bridge_ids,
|
|
.ops = &tegra_dsi_bridge_ops,
|
|
.probe = tegra_dsi_bridge_probe,
|
|
.plat_auto = sizeof(struct tegra_dc_plat),
|
|
.priv_auto = sizeof(struct tegra_dsi_priv),
|
|
};
|