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In warm reset conditions on OMAP36xx/AM/DM37xx the rom code incorrectly sets the DPLL4 clock input divider to /6.5 which is an invalid value unless the input clock is 13MHz. When a JTAG emulator is attached, a warm reset is necessary after the emulator gains control of the process. This results in a loss of serial output due to the invalid DPLL4 settings. This patch fixes the issue by resetting the DPLL4 clock input divider to /1 when the input clock is not 13MHz. AM/DM37x TRM section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only used when the input clock is 13MHz. Signed-off-by: Matt Porter <mporter@ti.com> |
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arm720t | ||
arm920t | ||
arm925t | ||
arm926ejs | ||
arm946es | ||
arm1136 | ||
arm1176 | ||
arm_intcm | ||
armv7 | ||
ixp | ||
lh7a40x | ||
pxa | ||
s3c44b0 | ||
sa1100 | ||
u-boot.lds |