Tien Fong Chee ee06c5390f ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS ... Bit[7-4] for both register seq2core and core2seq handshake in HPS are not required for triggering DDR re-calibration or resetting EMIF. So, ignoring these bits just for playing it safe. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>		2022-06-16 16:10:44 +08:00
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Kconfig	arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64	2021-03-08 10:59:10 +08:00
Makefile	ddr: altera: Add SDRAM driver for Intel N5X device	2021-08-25 13:47:05 +08:00
sdram_agilex.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00
sdram_arria10.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00
sdram_gen5.c	dm: Use access methods for dev/uclass private data	2021-01-05 12:24:40 -07:00
sdram_n5x.c	intel: n5x: ddr: update license	2022-06-15 17:48:22 +08:00
sdram_s10.c	WS cleanup: remove trailing empty lines	2021-09-30 08:08:56 -04:00
sdram_s10.h	ddr: altera: Restructure Stratix 10 SDRAM driver	2020-01-07 14:38:33 +01:00
sdram_soc64.c	ddr: altera: Add SDRAM driver for Intel N5X device	2021-08-25 13:47:05 +08:00
sdram_soc64.h	ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS	2022-06-16 16:10:44 +08:00
sequencer.c	drivers/ddr/altera/sequencer.c: Fix spelling of "resetting".	2022-01-13 07:57:50 -05:00
sequencer.h	ddr: altera: Add DDR2 support to Gen5 driver	2020-02-05 03:01:57 +01:00