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87e29878ca
This board runs a P5020 or P5040 chip, and utilizes an EEPROM with similar formatting to the Freescale P5020DS. Large amounts of this code were developed by Adrian Cox <adrian at humboldt dot co dot uk> Signed-off-by: Andy Fleming <afleming@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
188 lines
4.9 KiB
C
188 lines
4.9 KiB
C
/*
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* Based on corenet_ds ddr code
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <hwconfig.h>
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#include <asm/mmu.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 cpo;
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u32 write_data_delay;
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u32 force_2t;
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};
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/*
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* This table contains all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| clk| wrlvl | cpo |wrdata|2T
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* ranks| mhz|adjst| start | |delay |
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*/
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{4, 850, 4, 6, 0xff, 2, 0},
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{4, 950, 5, 7, 0xff, 2, 0},
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{4, 1050, 5, 8, 0xff, 2, 0},
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{4, 1250, 5, 10, 0xff, 2, 0},
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{4, 1350, 5, 11, 0xff, 2, 0},
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{4, 1666, 5, 12, 0xff, 2, 0},
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{2, 850, 5, 6, 0xff, 2, 0},
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{2, 1050, 5, 7, 0xff, 2, 0},
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{2, 1250, 4, 6, 0xff, 2, 0},
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{2, 1350, 5, 7, 0xff, 2, 0},
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{2, 1666, 5, 8, 0xff, 2, 0},
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{1, 1250, 4, 6, 0xff, 2, 0},
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{1, 1335, 4, 7, 0xff, 2, 0},
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{1, 1666, 4, 8, 0xff, 2, 0},
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{}
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};
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/*
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* The two slots have slightly different timing. The center values are good
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* for both slots. We use identical speed tables for them. In future use, if
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* DIMMs have fewer center values that require two separated tables, copy the
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* udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
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*/
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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udimm0,
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};
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static const struct board_specific_parameters rdimm0[] = {
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/*
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* memory controller 0
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* num| hi| clk| wrlvl | cpo |wrdata|2T
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* ranks| mhz|adjst| start | |delay |
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*/
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{4, 850, 4, 6, 0xff, 2, 0},
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{4, 950, 5, 7, 0xff, 2, 0},
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{4, 1050, 5, 8, 0xff, 2, 0},
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{4, 1250, 5, 10, 0xff, 2, 0},
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{4, 1350, 5, 11, 0xff, 2, 0},
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{4, 1666, 5, 12, 0xff, 2, 0},
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{2, 850, 4, 6, 0xff, 2, 0},
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{2, 1050, 4, 7, 0xff, 2, 0},
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{2, 1666, 4, 8, 0xff, 2, 0},
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{1, 850, 4, 5, 0xff, 2, 0},
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{1, 950, 4, 7, 0xff, 2, 0},
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{1, 1666, 4, 8, 0xff, 2, 0},
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{}
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};
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/*
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* The two slots have slightly different timing. See comments above.
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*/
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static const struct board_specific_parameters *rdimms[] = {
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rdimm0,
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rdimm0,
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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if (ctrl_num > 1) {
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printf("Wrong parameter for controller number %d", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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if (popts->registered_dimm_en)
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pbsp = rdimms[ctrl_num];
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else
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pbsp = udimms[ctrl_num];
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay =
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pbsp->write_data_delay;
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->twot_en = pbsp->force_2t;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found for data rate %lu MT/s!\nTrying to use the highest speed (%u) parameters\n",
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ddr_freq, pbsp_highest->datarate_mhz_high);
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popts->cpo_override = pbsp_highest->cpo;
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popts->write_data_delay = pbsp_highest->write_data_delay;
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popts->clk_adjust = pbsp_highest->clk_adjust;
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popts->wrlvl_start = pbsp_highest->wrlvl_start;
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popts->twot_en = pbsp_highest->force_2t;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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/*
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* Write leveling override
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*/
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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/*
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* Rtt and Rtt_WR override
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*/
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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/* DHC_EN =1, ODT = 60 Ohm */
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size;
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puts("Initializing....");
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if (!fsl_use_spd())
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panic("Cyrus only supports using SPD for DRAM\n");
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puts("using SPD\n");
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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debug(" DDR: ");
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return dram_size;
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}
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