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46 lines
1.3 KiB
Text
46 lines
1.3 KiB
Text
Notes on the Vibren PXA255 IDP.
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Chip select usage:
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CS0 - flash
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CS1 - alt flash (Mdoc or main flash)
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CS2 - high speed expansion bus
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CS3 - Media Q, low speed exp bus
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CS4 - low speed exp bus
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CS5 - low speed exp bus
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- IDE: offset 0x03000000 (abs: 0x17000000)
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- Eth: offset 0x03400000 (abs: 0x17400000)
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- core voltage latch: offset 0x03800000 (abs: 0x17800000)
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- CPLD: offset 0x03C00000 (abs: 0x17C00000)
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PCMCIA Power control
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MAX1602EE w/ code pulled high (Cirrus code)
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vx = 5v
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vy = 3v
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Bit pattern
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PWR 3,2,1,0
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vcc vpp A1VCC A0VCC A1VPP A0VPP
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=====================================================
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0 0 0 0 0 0 0x0
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3 (vy) 0 1 0 1 1 0xB
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3 (vy) 3 (vy) 1 0 0 1 0x9
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3 (vy) 12(12in) 1 0 1 0 0xA
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5 (vx) 0 0 1 1 1 0x7
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5 (vx) 5 (vx) 0 1 0 1 0x5
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5 (vx 12(12in) 0 1 1 0 0x6
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Display power sequencing:
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- VDD applied
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- within 1sec, activate scanning signals
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- wait at least 50mS - scanning signals must be active before activating DISP
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Signal mapping:
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Schematic LV8V31 signal name
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=========================================
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LCD_ENAVLCD DISP
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LCD_PWR Applies VDD to board
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Both of the above signals are controlled by the CPLD
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