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https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
340 lines
9.2 KiB
C
340 lines
9.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Cortina CS4315/CS4340 10G PHY drivers
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*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2018 NXP
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*
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <linux/ctype.h>
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#include <linux/string.h>
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#include <linux/err.h>
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#include <phy.h>
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#include <cortina.h>
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#ifdef CONFIG_SYS_CORTINA_FW_IN_NAND
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#include <nand.h>
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#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
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#include <spi_flash.h>
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#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
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#include <mmc.h>
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#endif
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#ifndef CONFIG_PHYLIB_10G
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#error The Cortina PHY needs 10G support
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#endif
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#ifndef CORTINA_NO_FW_UPLOAD
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struct cortina_reg_config cortina_reg_cfg[] = {
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/* CS4315_enable_sr_mode */
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{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
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{VILLA_MSEQ_OPTIONS, 0xf},
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{VILLA_MSEQ_PC, 0x0},
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{VILLA_MSEQ_BANKSELECT, 0x4},
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{VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
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{VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
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{VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
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{VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
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{VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
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{VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
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{VILLA_MSEQ_ENABLE_MSB, 0x0000},
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{VILLA_MSEQ_SPARE21_LSB, 0x6},
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{VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
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{VILLA_MSEQ_SPARE12_MSB, 0x0000},
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/*
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* to invert the receiver path, uncomment the next line
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* write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
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*
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* SPARE2_LSB is used to configure the device while in sr mode to
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* enable power savings and to use the optical module LOS signal.
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* in power savings mode, the internal prbs checker can not be used.
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* if the optical module LOS signal is used as an input to the micro
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* code, then the micro code will wait until the optical module
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* LOS = 0 before turning on the adaptive equalizer.
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* Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode
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* while setting bit 0 to 0 disables power savings mode.
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* Setting SPARE2_LSB bit 2 to 0 configures the device to use the
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* optical module LOS signal while setting bit 2 to 1 configures the
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* device so that it will ignore the optical module LOS SPARE2_LSB = 0
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*/
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/* enable power savings, ignore optical module LOS */
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{VILLA_MSEQ_SPARE2_LSB, 0x5},
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{VILLA_MSEQ_SPARE7_LSB, 0x1e},
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{VILLA_MSEQ_BANKSELECT, 0x4},
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{VILLA_MSEQ_SPARE9_LSB, 0x2},
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{VILLA_MSEQ_SPARE3_LSB, 0x0F53},
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{VILLA_MSEQ_SPARE3_MSB, 0x2006},
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{VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
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{VILLA_MSEQ_SPARE8_MSB, 0x0A46},
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{VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
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{VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
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{VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
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{VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
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{VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
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{VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
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{VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
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{VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
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{VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
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{VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2},
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{VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000},
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{VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF},
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{VILLA_MSEQ_POWER_DOWN_MSB, 0x0},
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{VILLA_MSEQ_CAL_RX_SLICER, 0x80},
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{VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f},
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{VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
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{VILLA_MSEQ_OPTIONS, 0x7},
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/* set up min value for ffe1 */
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{VILLA_MSEQ_COEF_INIT_SEL, 0x2},
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{VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41},
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/* CS4315_sr_rx_pre_eq_set_4in */
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{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
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{VILLA_MSEQ_OPTIONS, 0xf},
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{VILLA_MSEQ_BANKSELECT, 0x4},
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{VILLA_MSEQ_PC, 0x0},
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/* for lengths from 3.5 to 4.5inches */
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{VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306},
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{VILLA_MSEQ_SPARE25_LSB, 0x0306},
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{VILLA_MSEQ_SPARE21_LSB, 0x2},
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{VILLA_MSEQ_SPARE23_LSB, 0x2},
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{VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0},
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{VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
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{VILLA_MSEQ_OPTIONS, 0x7},
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/* CS4315_rx_drive_4inch */
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/* for length 4inches */
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{VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
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{VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
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{VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
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/* CS4315_tx_drive_4inch */
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/* for length 4inches */
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{VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
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{VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
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{VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
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};
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void cs4340_upload_firmware(struct phy_device *phydev)
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{
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char line_temp[0x50] = {0};
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char reg_addr[0x50] = {0};
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char reg_data[0x50] = {0};
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int i, line_cnt = 0, column_cnt = 0;
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struct cortina_reg_config fw_temp;
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char *addr = NULL;
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#if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
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defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
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addr = (char *)CONFIG_CORTINA_FW_ADDR;
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#elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
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int ret;
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size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
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addr = malloc(CONFIG_CORTINA_FW_LENGTH);
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ret = nand_read(get_nand_dev_by_index(0),
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(loff_t)CONFIG_CORTINA_FW_ADDR,
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&fw_length, (u_char *)addr);
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if (ret == -EUCLEAN) {
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printf("NAND read of Cortina firmware at 0x%x failed %d\n",
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CONFIG_CORTINA_FW_ADDR, ret);
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}
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#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
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int ret;
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struct spi_flash *ucode_flash;
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addr = malloc(CONFIG_CORTINA_FW_LENGTH);
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ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
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CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
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if (!ucode_flash) {
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puts("SF: probe for Cortina ucode failed\n");
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} else {
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ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR,
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CONFIG_CORTINA_FW_LENGTH, addr);
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if (ret)
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puts("SF: read for Cortina ucode failed\n");
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spi_flash_free(ucode_flash);
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}
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#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
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int dev = CONFIG_SYS_MMC_ENV_DEV;
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u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
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u32 blk = CONFIG_CORTINA_FW_ADDR / 512;
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struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
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if (!mmc) {
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puts("Failed to find MMC device for Cortina ucode\n");
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} else {
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addr = malloc(CONFIG_CORTINA_FW_LENGTH);
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printf("MMC read: dev # %u, block # %u, count %u ...\n",
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dev, blk, cnt);
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mmc_init(mmc);
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(void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
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addr);
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}
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#endif
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while (*addr != 'Q') {
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i = 0;
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while (*addr != 0x0a) {
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line_temp[i++] = *addr++;
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if (0x50 < i) {
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printf("Not found Cortina PHY ucode at 0x%p\n",
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(char *)CONFIG_CORTINA_FW_ADDR);
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return;
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}
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}
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addr++; /* skip '\n' */
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line_cnt++;
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column_cnt = i;
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line_temp[column_cnt] = '\0';
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if (CONFIG_CORTINA_FW_LENGTH < line_cnt)
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return;
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for (i = 0; i < column_cnt; i++) {
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if (isspace(line_temp[i++]))
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break;
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}
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memcpy(reg_addr, line_temp, i);
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memcpy(reg_data, &line_temp[i], column_cnt - i);
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strim(reg_addr);
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strim(reg_data);
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fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
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fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) &
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0xffff;
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phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
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}
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}
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#endif
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int cs4340_phy_init(struct phy_device *phydev)
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{
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#ifndef CORTINA_NO_FW_UPLOAD
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int timeout = 100; /* 100ms */
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#endif
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int reg_value;
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/*
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* Cortina phy has provision to store
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* phy firmware in attached dedicated EEPROM.
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* Boards designed with EEPROM attached to Cortina
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* does not require FW upload.
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*/
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#ifndef CORTINA_NO_FW_UPLOAD
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/* step1: BIST test */
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phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
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phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
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phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001);
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while (--timeout) {
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reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS);
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if (reg_value & mseq_edc_bist_done) {
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if (0 == (reg_value & mseq_edc_bist_fail))
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break;
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}
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udelay(1000);
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}
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if (!timeout) {
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printf("%s BIST mseq_edc_bist_done timeout!\n", __func__);
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return -1;
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}
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/* setp2: upload ucode */
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cs4340_upload_firmware(phydev);
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#endif
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reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
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if (reg_value) {
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debug("%s checksum status failed.\n", __func__);
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return -1;
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}
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return 0;
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}
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int cs4340_config(struct phy_device *phydev)
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{
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cs4340_phy_init(phydev);
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return 0;
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}
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int cs4340_probe(struct phy_device *phydev)
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{
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phydev->flags = PHY_FLAG_BROKEN_RESET;
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return 0;
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}
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int cs4340_startup(struct phy_device *phydev)
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{
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phydev->link = 1;
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/* For now just lie and say it's 10G all the time */
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phydev->speed = SPEED_10000;
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phydev->duplex = DUPLEX_FULL;
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return 0;
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}
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struct phy_driver cs4340_driver = {
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.name = "Cortina CS4315/CS4340",
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.uid = PHY_UID_CS4340,
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.mask = 0xfffffff0,
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.features = PHY_10G_FEATURES,
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.mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
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MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
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MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
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.config = &cs4340_config,
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.probe = &cs4340_probe,
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.startup = &cs4340_startup,
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.shutdown = &gen10g_shutdown,
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};
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int phy_cortina_init(void)
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{
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phy_register(&cs4340_driver);
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return 0;
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}
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int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
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{
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int phy_reg;
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/* Cortina PHY has non-standard offset of PHY ID registers */
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phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
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if (phy_reg < 0)
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return -EIO;
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*phy_id = (phy_reg & 0xffff) << 16;
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phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
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if (phy_reg < 0)
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return -EIO;
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*phy_id |= (phy_reg & 0xffff);
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if (*phy_id == PHY_UID_CS4340)
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return 0;
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/*
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* If Cortina PHY not detected,
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* try generic way to find PHY ID registers
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*/
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phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
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if (phy_reg < 0)
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return -EIO;
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*phy_id = (phy_reg & 0xffff) << 16;
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phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
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if (phy_reg < 0)
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return -EIO;
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*phy_id |= (phy_reg & 0xffff);
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return 0;
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}
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