mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 15:37:23 +00:00
167 lines
4.6 KiB
C
167 lines
4.6 KiB
C
/*
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/ic/sc520.h>
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#ifdef CONFIG_HW_WATCHDOG
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#include <watchdog.h>
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#endif
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#include "hardware.h"
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DECLARE_GLOBAL_DATA_PTR;
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#undef SC520_CDP_DEBUG
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#ifdef SC520_CDP_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
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void init_sc520_enet (void)
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{
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/* Set CPU Speed to 100MHz */
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sc520_mmcr->cpuctl = 0x01;
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gd->cpu_clk = 100000000;
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/* wait at least one millisecond */
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asm("movl $0x2000,%%ecx\n"
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"0: pushl %%ecx\n"
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"popl %%ecx\n"
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"loop 0b\n": : : "ecx");
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/* turn on the SDRAM write buffer */
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sc520_mmcr->dbctl = 0x11;
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/* turn on the cache and disable write through */
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asm("movl %%cr0, %%eax\n"
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"andl $0x9fffffff, %%eax\n"
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"movl %%eax, %%cr0\n" : : : "eax");
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}
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/*
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* Miscellaneous platform dependent initializations
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*/
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int board_init(void)
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{
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init_sc520_enet();
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sc520_mmcr->gpcsrt = 0x01; /* GP Chip Select Recovery Time */
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sc520_mmcr->gpcspw = 0x07; /* GP Chip Select Pulse Width */
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sc520_mmcr->gpcsoff = 0x00; /* GP Chip Select Offset */
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sc520_mmcr->gprdw = 0x05; /* GP Read pulse width */
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sc520_mmcr->gprdoff = 0x01; /* GP Read offset */
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sc520_mmcr->gpwrw = 0x05; /* GP Write pulse width */
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sc520_mmcr->gpwroff = 0x01; /* GP Write offset */
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sc520_mmcr->piodata15_0 = 0x0630; /* PIO15_PIO0 Data */
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sc520_mmcr->piodata31_16 = 0x2000; /* PIO31_PIO16 Data */
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sc520_mmcr->piodir31_16 = 0x2000; /* GPIO Direction */
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sc520_mmcr->piodir15_0 = 0x87b5; /* GPIO Direction */
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sc520_mmcr->piopfs31_16 = 0x0dfe; /* GPIO pin function 31-16 reg */
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sc520_mmcr->piopfs15_0 = 0x200a; /* GPIO pin function 15-0 reg */
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sc520_mmcr->cspfs = 0x00f8; /* Chip Select Pin Function Select */
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sc520_mmcr->par[2] = 0x200713f8; /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
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sc520_mmcr->par[3] = 0x2c0712f8; /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
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sc520_mmcr->par[4] = 0x300711f8; /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
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sc520_mmcr->par[5] = 0x340710f8; /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
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sc520_mmcr->par[6] = 0xe3ffc000; /* SDRAM (0x00000000, 128MB) */
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sc520_mmcr->par[7] = 0xaa3fd000; /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
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sc520_mmcr->par[8] = 0xca3fd100; /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
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sc520_mmcr->par[9] = 0x4203d900; /* SRAM (GPCS0, 0x19000000, 1MB) */
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sc520_mmcr->par[10] = 0x4e03d910; /* SRAM (GPCS3, 0x19100000, 1MB) */
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sc520_mmcr->par[11] = 0x50018100; /* DP-RAM (GPCS4, 0x18100000, 4kB) */
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sc520_mmcr->par[12] = 0x54020000; /* CFLASH1 (0x200000000, 4kB) */
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sc520_mmcr->par[13] = 0x5c020001; /* CFLASH2 (0x200010000, 4kB) */
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/* sc520_mmcr->par14 = 0x8bfff800; */ /* BOOTCS at 0x18000000 */
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/* sc520_mmcr->par15 = 0x38201000; */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
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/* Disable Watchdog */
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sc520_mmcr->wdtmrctl = 0x3333;
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sc520_mmcr->wdtmrctl = 0xcccc;
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sc520_mmcr->wdtmrctl = 0x0000;
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/* Chip Select Configuration */
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sc520_mmcr->bootcsctl = 0x0033;
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sc520_mmcr->romcs1ctl = 0x0615;
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sc520_mmcr->romcs2ctl = 0x0615;
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sc520_mmcr->adddecctl = 0x02;
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sc520_mmcr->uart1ctl = 0x07;
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sc520_mmcr->sysarbctl = 0x06;
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sc520_mmcr->sysarbmenb = 0x0003;
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/* Crystal is 33.000MHz */
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gd->bus_clk = 33000000;
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return 0;
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}
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int dram_init(void)
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{
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init_sc520_dram();
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return 0;
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}
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void show_boot_progress(int val)
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{
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uchar led_mask;
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led_mask = 0x00;
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if (val < 0)
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led_mask |= LED_ERR_BITMASK;
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led_mask |= (uchar)(val & 0x001f);
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outb(led_mask, LED_LATCH_ADDRESS);
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}
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int last_stage_init(void)
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{
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int minor;
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int major;
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major = minor = 0;
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printf("Serck Controls eNET\n");
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return 0;
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}
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ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
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{
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if (banknum == 0) { /* non-CFI boot flash */
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info->portwidth = FLASH_CFI_8BIT;
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info->chipwidth = FLASH_CFI_BY8;
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info->interface = FLASH_CFI_X8;
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return 1;
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} else
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return 0;
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}
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