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162a6f53a1
Add functionality to enable, set priority to the input events and to route to MCU ESM. On AM64x/AM62x devices, it is possible to route Main ESM0 error events to MCU ESM. When these error events are routed to MCU ESM high output, it can trigger the reset logic to reset the device, when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'. K3 based J7 devices (ex: J721e) also have ESM modules, and the changes to the driver does not impact those devices. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
135 lines
3 KiB
C
135 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Texas Instruments' K3 Error Signalling Module driver
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*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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* Tero Kristo <t-kristo@ti.com>
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#define ESM_SFT_RST 0x0c
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#define ESM_SFT_RST_KEY 0x0f
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#define ESM_EN 0x08
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#define ESM_EN_KEY 0x0f
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#define ESM_STS(i) (0x404 + (i) / 32 * 0x20)
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#define ESM_STS_MASK(i) (1 << ((i) % 32))
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#define ESM_PIN_EN_SET_OFFSET(i) (0x414 + (i) / 32 * 0x20)
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#define ESM_PIN_MASK(i) (1 << ((i) % 32))
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#define ESM_INTR_EN_SET_OFFSET(i) (0x408 + (i) / 32 * 0x20)
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#define ESM_INTR_MASK(i) (1 << ((i) % 32))
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#define ESM_INTR_PRIO_SET_OFFSET(i) (0x410 + (i) / 32 * 0x20)
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#define ESM_INTR_PRIO_MASK(i) (1 << ((i) % 32))
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static void esm_pin_enable(void __iomem *base, int pin)
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{
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u32 value;
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value = readl(base + ESM_PIN_EN_SET_OFFSET(pin));
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value |= ESM_PIN_MASK(pin);
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/* Enable event */
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writel(value, base + ESM_PIN_EN_SET_OFFSET(pin));
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}
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static void esm_intr_enable(void __iomem *base, int pin)
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{
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u32 value;
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value = readl(base + ESM_INTR_EN_SET_OFFSET(pin));
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value |= ESM_INTR_MASK(pin);
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/* Enable Interrupt event */
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writel(value, base + ESM_INTR_EN_SET_OFFSET(pin));
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}
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static void esm_intr_prio_set(void __iomem *base, int pin)
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{
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u32 value;
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value = readl(base + ESM_INTR_PRIO_SET_OFFSET(pin));
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value |= ESM_INTR_PRIO_MASK(pin);
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/* Set to priority */
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writel(value, base + ESM_INTR_PRIO_SET_OFFSET(pin));
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}
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static void esm_clear_raw_status(void __iomem *base, int pin)
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{
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u32 value;
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value = readl(base + ESM_STS(pin));
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value |= ESM_STS_MASK(pin);
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/* Clear Event status */
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writel(value, base + ESM_STS(pin));
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}
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/**
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* k3_esm_probe: configures ESM based on DT data
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*
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* Parses ESM info from device tree, and configures the module accordingly.
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*/
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static int k3_esm_probe(struct udevice *dev)
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{
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int ret;
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void __iomem *base;
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int num_pins;
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u32 *pins;
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int i;
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base = dev_remap_addr_index(dev, 0);
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if (!base)
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return -ENODEV;
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num_pins = dev_read_size(dev, "ti,esm-pins");
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if (num_pins < 0) {
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dev_err(dev, "ti,esm-pins property missing or invalid: %d\n",
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num_pins);
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return num_pins;
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}
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num_pins /= sizeof(u32);
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pins = kmalloc(num_pins * sizeof(u32), __GFP_ZERO);
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if (!pins)
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return -ENOMEM;
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ret = dev_read_u32_array(dev, "ti,esm-pins", pins, num_pins);
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if (ret < 0) {
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dev_err(dev, "failed to read ti,esm-pins property: %d\n",
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ret);
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goto free_pins;
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}
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/* Clear any pending events */
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writel(ESM_SFT_RST_KEY, base + ESM_SFT_RST);
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for (i = 0; i < num_pins; i++) {
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esm_intr_prio_set(base, pins[i]);
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esm_clear_raw_status(base, pins[i]);
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esm_pin_enable(base, pins[i]);
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esm_intr_enable(base, pins[i]);
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}
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/* Enable ESM */
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writel(ESM_EN_KEY, base + ESM_EN);
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free_pins:
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kfree(pins);
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return ret;
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}
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static const struct udevice_id k3_esm_ids[] = {
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{ .compatible = "ti,j721e-esm" },
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{}
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};
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U_BOOT_DRIVER(k3_esm) = {
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.name = "k3_esm",
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.of_match = k3_esm_ids,
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.id = UCLASS_MISC,
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.probe = k3_esm_probe,
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};
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