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https://github.com/AsahiLinux/u-boot
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ed54e62125
* Enable long help on CMC PU2 board; fix reset issue; increase CPU speed from 179 to 207 MHz.
202 lines
4.8 KiB
C
202 lines
4.8 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* CPU specific code
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
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#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
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#endif
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/* read co-processor 15, register #1 (control register) */
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static unsigned long read_p15_c1(void)
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{
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unsigned long value;
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__asm__ __volatile__(
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"mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
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: "=r" (value)
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:
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: "memory");
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/*printf("p15/c1 is = %08lx\n", value); */
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return value;
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}
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/* write to co-processor 15, register #1 (control register) */
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static void write_p15_c1(unsigned long value)
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{
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/*printf("write %08lx to p15/c1\n", value); */
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__asm__ __volatile__(
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"mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
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: "=r" (value)
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:
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: "memory");
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read_p15_c1();
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}
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static void cp_delay(void)
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{
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volatile int i;
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/* copro seems to need some delay between reading and writing */
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for (i=0; i<100; i++);
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}
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/* See also ARM Ref. Man. */
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#define C1_MMU (1<<0) /* mmu off/on */
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#define C1_ALIGN (1<<1) /* alignment faults off/on */
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#define C1_IDC (1<<2) /* icache and/or dcache off/on */
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#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */
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#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
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#define C1_SYS_PROT (1<<8) /* system protection */
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#define C1_ROM_PROT (1<<9) /* ROM protection */
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#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
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int cpu_init(void)
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{
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/*
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* setup up stacks if necessary
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*/
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#ifdef CONFIG_USE_IRQ
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DECLARE_GLOBAL_DATA_PTR;
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IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
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FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
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#endif
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return 0;
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}
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int cleanup_before_linux(void)
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{
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/*
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* this function is called just before we call linux
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* it prepares the processor for linux
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*
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* we turn off caches etc ...
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* and we set the CPU-speed to 73 MHz - see start.S for details
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*/
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disable_interrupts();
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return 0;
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}
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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#ifdef CFG_SOFT_RESET
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extern void reset_cpu(ulong addr);
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disable_interrupts();
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reset_cpu(0);
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#else
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#ifdef CONFIG_DBGU
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AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
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#endif
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#ifdef CONFIG_USART0
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AT91PS_USART us = AT91C_BASE_US0;
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#endif
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#ifdef CONFIG_USART1
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AT91PS_USART us = AT91C_BASE_US1;
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#endif
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AT91PS_PIO pio = AT91C_BASE_PIOA;
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/*shutdown the console to avoid strange chars during reset */
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us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
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#ifdef CONFIG_AT91RM9200DK
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/* Clear PA19 to trigger the hard reset */
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pio->PIO_CODR = 0x00080000;
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pio->PIO_OER = 0x00080000;
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pio->PIO_PER = 0x00080000;
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#endif
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#ifdef CONFIG_CMC_PU2
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/* this is the way Linux does it */
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#define AT91C_ST_RSTEN (0x1 << 16)
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#define AT91C_ST_EXTEN (0x1 << 17)
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#define AT91C_ST_WDRST (0x1 << 0)
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/* watchdog mode register */
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#define ST_WDMR *((unsigned long *)0xfffffd08)
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/* system clock control register */
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#define ST_CR *((unsigned long *)0xfffffd00)
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ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
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ST_CR = AT91C_ST_WDRST;
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/* Never reached */
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#endif
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#endif
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return 0;
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}
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void icache_enable(void)
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{
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ulong reg;
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reg = read_p15_c1();
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cp_delay();
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write_p15_c1(reg | C1_IDC);
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}
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void icache_disable(void)
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{
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ulong reg;
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reg = read_p15_c1();
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cp_delay();
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write_p15_c1(reg & ~C1_IDC);
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}
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int icache_status(void)
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{
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return (read_p15_c1() & C1_IDC) != 0;
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return 0;
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}
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void dcache_enable(void)
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{
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ulong reg;
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reg = read_p15_c1();
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cp_delay();
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write_p15_c1(reg | C1_IDC);
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}
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void dcache_disable(void)
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{
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ulong reg;
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reg = read_p15_c1();
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cp_delay();
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write_p15_c1(reg & ~C1_IDC);
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}
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int dcache_status(void)
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{
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return (read_p15_c1() & C1_IDC) != 0;
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return 0;
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}
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