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https://github.com/AsahiLinux/u-boot
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3eb90bad65
According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
168 lines
4.1 KiB
C
168 lines
4.1 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/arch/kirkwood.h>
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#define UBOOT_CNTR 0 /* counter to use for uboot timer */
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/* Timer reload and current value registers */
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struct kwtmr_val {
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u32 reload; /* Timer reload reg */
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u32 val; /* Timer value reg */
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};
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/* Timer registers */
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struct kwtmr_registers {
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u32 ctrl; /* Timer control reg */
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u32 pad[3];
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struct kwtmr_val tmr[2];
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u32 wdt_reload;
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u32 wdt_val;
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};
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struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
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/*
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* ARM Timers Registers Map
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*/
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#define CNTMR_CTRL_REG &kwtmr_regs->ctrl
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#define CNTMR_RELOAD_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].reload
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#define CNTMR_VAL_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].val
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/*
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* ARM Timers Control Register
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* CPU_TIMERS_CTRL_REG (CTCR)
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*/
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#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
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#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
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#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
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#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
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#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
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#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
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#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
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#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
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/*
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* ARM Timer\Watchdog Reload Register
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* CNTMR_RELOAD_REG (TRR)
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*/
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#define TRG_ARM_TIMER_REL_OFFS 0
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#define TRG_ARM_TIMER_REL_MASK 0xffffffff
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/*
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* ARM Timer\Watchdog Register
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* CNTMR_VAL_REG (TVRG)
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*/
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#define TVR_ARM_TIMER_OFFS 0
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#define TVR_ARM_TIMER_MASK 0xffffffff
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#define TVR_ARM_TIMER_MAX 0xffffffff
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#define TIMER_LOAD_VAL 0xffffffff
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#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
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(CONFIG_SYS_TCLK / 1000))
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static ulong timestamp;
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static ulong lastdec;
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void reset_timer_masked(void)
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{
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/* reset time */
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lastdec = READ_TIMER;
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timestamp = 0;
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}
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ulong get_timer_masked(void)
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{
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ulong now = READ_TIMER;
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if (lastdec >= now) {
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/* normal mode */
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timestamp += lastdec - now;
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} else {
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/* we have an overflow ... */
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timestamp += lastdec +
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(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
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}
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lastdec = now;
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return timestamp;
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}
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void reset_timer(void)
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{
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reset_timer_masked();
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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void set_timer(ulong t)
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{
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timestamp = t;
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}
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void __udelay(unsigned long usec)
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{
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uint current;
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ulong delayticks;
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current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
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delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
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if (current < delayticks) {
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delayticks -= current;
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while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
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while ((TIMER_LOAD_VAL - delayticks) <
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readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
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} else {
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while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
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(current - delayticks)) ;
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}
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}
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/*
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* init the counter
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*/
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int timer_init(void)
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{
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unsigned int cntmrctrl;
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/* load value into timer */
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writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
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writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
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/* enable timer in auto reload mode */
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cntmrctrl = readl(CNTMR_CTRL_REG);
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cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
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cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
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writel(cntmrctrl, CNTMR_CTRL_REG);
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/* init the timestamp and lastdec value */
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reset_timer_masked();
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return 0;
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}
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