mirror of
https://github.com/AsahiLinux/u-boot
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304 lines
8 KiB
C
304 lines
8 KiB
C
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <libfdt.h>
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#include <mpc8xx.h>
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#include <hwconfig.h>
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#include <i2c.h>
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#include "../common/kup.h"
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#include <asm/io.h>
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static unsigned char swapbyte(unsigned char c);
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static int read_diag(void);
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DECLARE_GLOBAL_DATA_PTR;
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/* ----------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
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0x1FF77C47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ----------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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uchar rev,mod,tmp,pcf,ak_rev,ak_mod;
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/*
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* Init ChipSelect #4 (CAN + HW-Latch)
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*/
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out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
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out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
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/*
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* Init ChipSelect #5 (S1D13768)
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*/
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out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5);
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out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5);
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tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR));
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rev = (tmp & 0xF8) >> 3;
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mod = (tmp & 0x07);
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (read_diag())
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gd->flags &= ~GD_FLG_SILENT;
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printf("Board: KUP4K Rev %d.%d AK:",rev,mod);
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/*
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* TI Application report: Before using the IO as an input,
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* a high must be written to the IO first
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*/
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pcf = 0xFF;
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i2c_write(0x21, 0, 0 , &pcf, 1);
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if (i2c_read(0x21, 0, 0, &pcf, 1)) {
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puts("n/a\n");
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} else {
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ak_rev = (pcf & 0xF8) >> 3;
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ak_mod = (pcf & 0x07);
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printf("%d.%d\n", ak_rev, ak_mod);
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}
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return 0;
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}
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/* ----------------------------------------------------------------------- */
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size = 0;
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uchar *latch,rev,mod,tmp;
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/*
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* Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision
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* Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB
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*/
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out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
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out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
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latch = (uchar *)0x90000200;
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tmp = swapbyte(*latch);
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rev = (tmp & 0xF8) >> 3;
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mod = (tmp & 0x07);
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upmconfig(UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
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out_be32(&memctl->memc_mar, 0x00000088);
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/* no refresh yet */
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if(rev >= 7) {
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out_be32(&memctl->memc_mamr,
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CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)));
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} else {
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out_be32(&memctl->memc_mamr,
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CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)));
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}
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udelay(200);
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/* perform SDRAM initializsation sequence */
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/* SDRAM bank 0 */
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out_be32(&memctl->memc_mcr, 0x80002105);
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
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udelay(1);
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/* SDRAM bank 1 */
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out_be32(&memctl->memc_mcr, 0x80004105);
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
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udelay(1);
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/* SDRAM bank 2 */
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out_be32(&memctl->memc_mcr, 0x80006105);
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
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udelay(1);
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setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
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udelay(1000);
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out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
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udelay(1000);
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if(rev >= 7) {
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size = 32 * 3 * 1024 * 1024;
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out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL);
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out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL);
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out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL);
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out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL);
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out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL);
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out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL);
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} else {
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size = 16 * 3 * 1024 * 1024;
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out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL);
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out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL);
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out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL);
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out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL);
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out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL);
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out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL);
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}
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return (size);
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}
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/* ----------------------------------------------------------------------- */
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int misc_init_r(void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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#ifdef CONFIG_IDE_LED
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/* Configure PA8 as output port */
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setbits_be16(&immap->im_ioport.iop_padir, PA_8);
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setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
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clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
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setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
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#endif
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load_sernum_ethaddr();
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setenv("hw","4k");
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poweron_key();
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return (0);
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}
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static int read_diag(void)
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{
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int diag;
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4); /* input */
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clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
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setbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* output */
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clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
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setbits_be16(&immr->im_ioport.iop_pcdat, PC_5); /* 1 */
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udelay(500);
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if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) {
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clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */
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udelay(500);
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if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4)
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diag = 0;
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else
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diag = 1;
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} else {
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diag = 0;
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}
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clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* input */
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return (diag);
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}
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static unsigned char swapbyte(unsigned char c)
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{
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unsigned char result = 0;
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int i = 0;
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for(i = 0; i < 8; ++i) {
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result = result << 1;
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result |= (c & 1);
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c = c >> 1;
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}
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return result;
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}
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/*
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* Device Tree Support
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*/
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
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