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The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.
This driver requires two CONFIG macros:
- CONFIG_SPL_NAND_DENALI
Define to enable this driver.
- CONFIG_SYS_NAND_BAD_BLOCK_POS
Specify bad block mark position in the oob space. Typically 0.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>
42 lines
1 KiB
Text
42 lines
1 KiB
Text
menu "NAND Device Support"
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if !SPL_BUILD
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config NAND_DENALI
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bool "Support Denali NAND controller"
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help
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Enable support for the Denali NAND controller.
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config SYS_NAND_DENALI_64BIT
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bool "Use 64-bit variant of Denali NAND controller"
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depends on NAND_DENALI
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help
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The Denali NAND controller IP has some variations in terms of
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the bus interface. The DMA setup sequence is completely differenct
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between 32bit / 64bit AXI bus variants.
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If your Denali NAND controller is the 64-bit variant, say Y.
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Otherwise (32 bit), say N.
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config NAND_DENALI_SPARE_AREA_SKIP_BYTES
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int "Number of bytes skipped in OOB area"
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depends on NAND_DENALI
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range 0 63
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help
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This option specifies the number of bytes to skip from the beginning
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of OOB area before last ECC sector data starts. This is potentially
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used to preserve the bad block marker in the OOB area.
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endif
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if SPL_BUILD
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config SPL_NAND_DENALI
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bool "Support Denali NAND controller for SPL"
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help
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This is a small implementation of the Denali NAND controller
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for use on SPL.
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endif
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endmenu
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