mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-07 05:34:28 +00:00
67f9f11f19
In pre-reloc stage, U-Boot marks cacheable the DDR limited by the new config CONFIG_DDR_CACHEABLE_SIZE. This patch allows to avoid any speculative access to DDR protected by firewall and used by OP-TEE; the "no-map" reserved memory node in DT are assumed after this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. Without security, in basic boot, the value is equal to STM32_DDR_SIZE. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
154 lines
3 KiB
C
154 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <spl.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/libfdt.h>
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u32 spl_boot_device(void)
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{
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u32 boot_mode;
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boot_mode = get_bootmode();
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switch (boot_mode) {
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case BOOT_FLASH_SD_1:
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case BOOT_FLASH_EMMC_1:
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return BOOT_DEVICE_MMC1;
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case BOOT_FLASH_SD_2:
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case BOOT_FLASH_EMMC_2:
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return BOOT_DEVICE_MMC2;
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case BOOT_SERIAL_UART_1:
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case BOOT_SERIAL_UART_2:
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case BOOT_SERIAL_UART_3:
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case BOOT_SERIAL_UART_4:
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case BOOT_SERIAL_UART_5:
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case BOOT_SERIAL_UART_6:
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case BOOT_SERIAL_UART_7:
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case BOOT_SERIAL_UART_8:
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return BOOT_DEVICE_UART;
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case BOOT_SERIAL_USB_OTG:
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return BOOT_DEVICE_USB;
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case BOOT_FLASH_NAND_FMC:
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return BOOT_DEVICE_NAND;
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case BOOT_FLASH_NOR_QSPI:
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return BOOT_DEVICE_SPI;
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case BOOT_FLASH_SPINAND_1:
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return BOOT_DEVICE_NONE; /* SPINAND not supported in SPL */
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}
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return BOOT_DEVICE_MMC1;
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}
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u32 spl_mmc_boot_mode(const u32 boot_device)
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{
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return MMCSD_MODE_RAW;
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}
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int spl_mmc_boot_partition(const u32 boot_device)
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{
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switch (boot_device) {
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case BOOT_DEVICE_MMC1:
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return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION;
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case BOOT_DEVICE_MMC2:
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return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2;
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default:
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return -EINVAL;
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}
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}
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#ifdef CONFIG_SPL_DISPLAY_PRINT
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void spl_display_print(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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const char *model;
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/* same code than show_board_info() but not compiled for SPL
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* see CONFIG_DISPLAY_BOARDINFO & common/board_info.c
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*/
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model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
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if (model)
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printf("Model: %s\n", model);
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}
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#endif
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__weak int board_early_init_f(void)
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{
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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arch_cpu_init();
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device(UCLASS_CLK, 0, &dev);
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if (ret) {
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debug("Clock init failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device(UCLASS_RESET, 0, &dev);
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if (ret) {
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debug("Reset init failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
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if (ret) {
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debug("%s: Cannot find pinctrl device\n", __func__);
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hang();
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}
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/* enable console uart printing */
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preloader_console_init();
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ret = board_early_init_f();
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if (ret) {
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debug("board_early_init_f() failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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printf("DRAM init failed: %d\n", ret);
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hang();
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}
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/*
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* activate cache on DDR only when DDR is fully initialized
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* to avoid speculative access and issue in get_ram_size()
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*/
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if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
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CONFIG_DDR_CACHEABLE_SIZE,
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DCACHE_DEFAULT_OPTION);
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}
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void spl_board_prepare_for_boot(void)
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{
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dcache_disable();
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}
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void spl_board_prepare_for_linux(void)
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{
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dcache_disable();
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}
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