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https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
259 lines
6.2 KiB
C
259 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* SAMSUNG EXYNOS5 USB HOST XHCI Controller
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*
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* Copyright (C) 2012 Samsung Electronics Co.Ltd
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* Vivek Gautam <gautam.vivek@samsung.com>
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* Vikas Sajjan <vikas.sajjan@samsung.com>
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*/
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/*
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* This file is a conglomeration for DWC3-init sequence and further
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* exynos5 specific PHY-init sequence.
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <malloc.h>
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#include <usb.h>
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#include <watchdog.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/power.h>
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#include <asm/arch/xhci-exynos.h>
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#include <asm/gpio.h>
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#include <linux/errno.h>
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#include <linux/compat.h>
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#include <linux/usb/dwc3.h>
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#include "xhci.h"
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/* Declare global data pointer */
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DECLARE_GLOBAL_DATA_PTR;
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struct exynos_xhci_platdata {
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fdt_addr_t hcd_base;
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fdt_addr_t phy_base;
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struct gpio_desc vbus_gpio;
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};
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/**
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* Contains pointers to register base addresses
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* for the usb controller.
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*/
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struct exynos_xhci {
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struct usb_platdata usb_plat;
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struct xhci_ctrl ctrl;
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struct exynos_usb3_phy *usb3_phy;
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struct xhci_hccr *hcd;
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struct dwc3 *dwc3_reg;
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};
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static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
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{
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struct exynos_xhci_platdata *plat = dev_get_platdata(dev);
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const void *blob = gd->fdt_blob;
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unsigned int node;
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int depth;
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/*
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* Get the base address for XHCI controller from the device node
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*/
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plat->hcd_base = devfdt_get_addr(dev);
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if (plat->hcd_base == FDT_ADDR_T_NONE) {
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debug("Can't get the XHCI register base address\n");
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return -ENXIO;
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}
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depth = 0;
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node = fdtdec_next_compatible_subnode(blob, dev_of_offset(dev),
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COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth);
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if (node <= 0) {
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debug("XHCI: Can't get device node for usb3-phy controller\n");
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return -ENODEV;
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}
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/*
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* Get the base address for usbphy from the device node
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*/
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plat->phy_base = fdtdec_get_addr(blob, node, "reg");
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if (plat->phy_base == FDT_ADDR_T_NONE) {
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debug("Can't get the usbphy register address\n");
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return -ENXIO;
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}
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/* Vbus gpio */
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gpio_request_by_name(dev, "samsung,vbus-gpio", 0,
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&plat->vbus_gpio, GPIOD_IS_OUT);
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return 0;
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}
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static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
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{
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u32 reg;
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/* enabling usb_drd phy */
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set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
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/* Reset USB 3.0 PHY */
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writel(0x0, &phy->phy_reg0);
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clrbits_le32(&phy->phy_param0,
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/* Select PHY CLK source */
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PHYPARAM0_REF_USE_PAD |
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/* Set Loss-of-Signal Detector sensitivity */
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PHYPARAM0_REF_LOSLEVEL_MASK);
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setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
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writel(0x0, &phy->phy_resume);
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/*
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* Setting the Frame length Adj value[6:1] to default 0x20
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* See xHCI 1.0 spec, 5.2.4
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*/
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setbits_le32(&phy->link_system,
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LINKSYSTEM_XHCI_VERSION_CONTROL |
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LINKSYSTEM_FLADJ(0x20));
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/* Set Tx De-Emphasis level */
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clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
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setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
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setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
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/* PHYTEST POWERDOWN Control */
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clrbits_le32(&phy->phy_test,
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PHYTEST_POWERDOWN_SSP |
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PHYTEST_POWERDOWN_HSP);
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/* UTMI Power Control */
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writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
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/* Use core clock from main PLL */
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reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
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/* Default 24Mhz crystal clock */
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PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
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PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
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PHYCLKRST_SSC_REFCLKSEL(0x88) |
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/* Force PortReset of PHY */
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PHYCLKRST_PORTRESET |
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/* Digital power supply in normal operating mode */
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PHYCLKRST_RETENABLEN |
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/* Enable ref clock for SS function */
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PHYCLKRST_REF_SSP_EN |
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/* Enable spread spectrum */
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PHYCLKRST_SSC_EN |
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/* Power down HS Bias and PLL blocks in suspend mode */
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PHYCLKRST_COMMONONN;
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writel(reg, &phy->phy_clk_rst);
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/* giving time to Phy clock to settle before resetting */
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udelay(10);
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reg &= ~PHYCLKRST_PORTRESET;
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writel(reg, &phy->phy_clk_rst);
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}
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static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy)
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{
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setbits_le32(&phy->phy_utmi,
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PHYUTMI_OTGDISABLE |
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PHYUTMI_FORCESUSPEND |
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PHYUTMI_FORCESLEEP);
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clrbits_le32(&phy->phy_clk_rst,
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PHYCLKRST_REF_SSP_EN |
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PHYCLKRST_SSC_EN |
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PHYCLKRST_COMMONONN);
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/* PHYTEST POWERDOWN Control to remove leakage current */
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setbits_le32(&phy->phy_test,
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PHYTEST_POWERDOWN_SSP |
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PHYTEST_POWERDOWN_HSP);
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/* disabling usb_drd phy */
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set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE);
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}
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static int exynos_xhci_core_init(struct exynos_xhci *exynos)
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{
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int ret;
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exynos5_usb3_phy_init(exynos->usb3_phy);
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ret = dwc3_core_init(exynos->dwc3_reg);
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if (ret) {
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debug("failed to initialize core\n");
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return -EINVAL;
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}
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/* We are hard-coding DWC3 core to Host Mode */
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dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
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return 0;
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}
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static void exynos_xhci_core_exit(struct exynos_xhci *exynos)
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{
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exynos5_usb3_phy_exit(exynos->usb3_phy);
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}
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static int xhci_usb_probe(struct udevice *dev)
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{
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struct exynos_xhci_platdata *plat = dev_get_platdata(dev);
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struct exynos_xhci *ctx = dev_get_priv(dev);
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struct xhci_hcor *hcor;
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int ret;
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ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
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ctx->usb3_phy = (struct exynos_usb3_phy *)plat->phy_base;
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ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
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hcor = (struct xhci_hcor *)((uint32_t)ctx->hcd +
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HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
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/* setup the Vbus gpio here */
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if (dm_gpio_is_valid(&plat->vbus_gpio))
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dm_gpio_set_value(&plat->vbus_gpio, 1);
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ret = exynos_xhci_core_init(ctx);
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if (ret) {
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puts("XHCI: failed to initialize controller\n");
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return -EINVAL;
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}
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return xhci_register(dev, ctx->hcd, hcor);
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}
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static int xhci_usb_remove(struct udevice *dev)
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{
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struct exynos_xhci *ctx = dev_get_priv(dev);
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int ret;
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ret = xhci_deregister(dev);
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if (ret)
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return ret;
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exynos_xhci_core_exit(ctx);
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return 0;
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}
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static const struct udevice_id xhci_usb_ids[] = {
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{ .compatible = "samsung,exynos5250-xhci" },
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{ }
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};
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U_BOOT_DRIVER(usb_xhci) = {
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.name = "xhci_exynos",
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.id = UCLASS_USB,
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.of_match = xhci_usb_ids,
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.ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
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.probe = xhci_usb_probe,
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.remove = xhci_usb_remove,
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.ops = &xhci_usb_ops,
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.platdata_auto_alloc_size = sizeof(struct exynos_xhci_platdata),
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.priv_auto_alloc_size = sizeof(struct exynos_xhci),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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