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1b4ca865b2
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but
similar enough to reuse code. Introduce a new CPG library, factor out
the SD clock and RPC clock handling and hook them to the generic Gen3
CPG driver so we have an equal state.
Based on Linux commit [1] and [2] by Wolfram Sang
[1] 8bb67d87346a ("clk: renesas: rcar-gen3: Factor out CPG library")
[2] 6f21d145b90f ("clk: renesas: cpg-lib: Move RPC clock registration to
the library")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
- Rebase on changes to
clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
- Use u32_encode_bits/GENMASK bitfield ops
33 lines
1.2 KiB
C
33 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* R-Car Gen3 Clock Pulse Generator Library
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*
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* Copyright (C) 2015-2018 Glider bvba
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* Copyright (C) 2019 Renesas Electronics Corp.
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*
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* Based on clk-rcar-gen3.c
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*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#ifndef __CLK_RENESAS_RCAR_CPG_LIB_H__
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#define __CLK_RENESAS_RCAR_CPG_LIB_H__
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s64 rcar_clk_get_rate64_div_table(unsigned int parent, u64 parent_rate,
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void __iomem *reg, const u32 mask,
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const struct clk_div_table *table, char *name);
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int rcar_clk_set_rate64_div_table(unsigned int parent, u64 parent_rate, ulong rate,
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void __iomem *reg, const u32 mask,
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const struct clk_div_table *table, char *name);
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s64 rcar_clk_get_rate64_sdh(unsigned int parent, u64 parent_rate, void __iomem *reg);
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s64 rcar_clk_get_rate64_sd(unsigned int parent, u64 parent_rate, void __iomem *reg);
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s64 rcar_clk_get_rate64_rpc(unsigned int parent, u64 parent_rate, void __iomem *reg);
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u64 rcar_clk_get_rate64_rpcd2(unsigned int parent, u64 parent_rate);
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int rcar_clk_set_rate64_sdh(unsigned int parent, u64 parent_rate, ulong rate,
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void __iomem *reg);
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int rcar_clk_set_rate64_sd(unsigned int parent, u64 parent_rate, ulong rate,
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void __iomem *reg);
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#endif
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