Leo Yu-Chi Liang f4512618ca riscv: ae350: Fix XIP config boot failure ... The booting flow is SPL -> OpenSBI -> U-Boot. The boot hart may change after OpenSBI and may not always be hart0, so wrap the related branch instruction with M-MODE. Current DTB setup for XIP is not valid. There is no chance for CONFIG_SYS_FDT_BASE, the DTB address used in XIP mode, to be returned. Fix this. Fixes: 2e8d2f8843 ("riscv: Remove OF_PRIOR_STAGE from RISC-V boards") Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2022-08-11 18:46:07 +08:00
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ax25	riscv: ae350: enable Coherence Manager for ae350	2021-10-07 16:08:23 +08:00
fu540	board: sifive: use ccache driver instead of helper function	2021-09-07 10:34:29 +08:00
fu740	riscv: Enable SPI flash env for SiFive Unmatched.	2021-12-02 16:43:56 +08:00
generic	riscv: qemu: Switch to use binman to generate u-boot.itb	2021-05-19 17:01:51 +08:00
cpu.c	event: Convert arch_cpu_init_dm() to use events	2022-03-10 08:28:36 -05:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: ae350: Fix XIP config boot failure	2022-08-11 18:46:07 +08:00
u-boot-spl.lds	linker_lists: Rename sections to remove . prefix	2022-06-23 12:58:18 -04:00
u-boot.lds	linker_lists: Rename sections to remove . prefix	2022-06-23 12:58:18 -04:00