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u-boot/board/altera/arria5-socdk
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Chin Liang See 0db1ac47ee arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1 
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27 08:03:08 +02:00
..
qts arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1 2016-10-27 08:03:08 +02:00
MAINTAINERS arm: socfpga: update MAINTAINERS' file for cyclone5_socdk and arria5_socdk 2015-09-23 03:55:28 +02:00
Makefile arm: socfpga: Split Altera socfpga into AV and CV SoCDK 2015-08-23 11:56:19 +02:00
socfpga.c arm: socfpga: Drop the board boilerplate 2015-12-20 03:36:51 +01:00