mirror of
https://github.com/AsahiLinux/u-boot
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257 lines
6.4 KiB
C
257 lines
6.4 KiB
C
/*
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* (C) Copyright 2006
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* Heiko Schocher, DENX Software Engineering, hs@denx.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/*
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* Altera FPGA configuration support for the ALPR computer from prodrive
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*/
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#include <common.h>
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#include <altera.h>
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#include <ACEX1K.h>
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#include <command.h>
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#include <asm-ppc/processor.h>
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#include <ppc440.h>
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#include "fpga.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_FPGA)
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#ifdef FPGA_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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static unsigned long regval;
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#define SET_GPIO_REG_0(reg, bit) { \
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regval = in32(reg); \
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regval &= ~(0x80000000 >> bit); \
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out32(reg, regval); \
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}
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#define SET_GPIO_REG_1(reg, bit) { \
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regval = in32(reg); \
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regval |= (0x80000000 >> bit); \
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out32(reg, regval); \
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}
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#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
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#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
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#define FPGA_PRG (0x80000000 >> CONFIG_SYS_GPIO_PROG_EN)
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#define FPGA_CONFIG (0x80000000 >> CONFIG_SYS_GPIO_CONFIG)
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#define FPGA_DATA (0x80000000 >> CONFIG_SYS_GPIO_DATA)
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#define FPGA_CLK (0x80000000 >> CONFIG_SYS_GPIO_CLK)
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#define OLD_VAL (FPGA_PRG | FPGA_CONFIG)
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#define SET_FPGA(data) out32(GPIO0_OR, data)
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#define FPGA_WRITE_1 { \
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SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \
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SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
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#define FPGA_WRITE_0 { \
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SET_FPGA(OLD_VAL | 0 | 0 ); /* set data to 0 */ \
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SET_FPGA(OLD_VAL | FPGA_CLK | 0 );} /* set data to 1 */
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/* Plattforminitializations */
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/* Here we have to set the FPGA Chain */
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/* PROGRAM_PROG_EN = HIGH */
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/* PROGRAM_SEL_DPR = LOW */
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int fpga_pre_fn (int cookie)
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{
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unsigned long reg;
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reg = in32(GPIO0_IR);
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/* Enable the FPGA Chain */
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
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SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN);
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR);
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SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR));
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/* initialize the GPIO Pins */
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/* output */
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SET_GPIO_0(CONFIG_SYS_GPIO_CLK);
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK);
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/* output */
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SET_GPIO_0(CONFIG_SYS_GPIO_DATA);
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA);
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/* First we set STATUS to 0 then as an input */
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
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SET_GPIO_0(CONFIG_SYS_GPIO_STATUS);
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SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
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/* output */
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG);
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SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
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/* input */
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SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON);
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SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON);
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/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
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SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
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return FPGA_SUCCESS;
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}
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/* Set the state of CONFIG Pin */
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int fpga_config_fn (int assert_config, int flush, int cookie)
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{
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if (assert_config) {
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SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG);
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} else {
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SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
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}
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return FPGA_SUCCESS;
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}
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/* Returns the state of STATUS Pin */
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int fpga_status_fn (int cookie)
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{
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unsigned long reg;
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reg = in32(GPIO0_IR);
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if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) {
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PRINTF("STATUS = HIGH\n");
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return FPGA_FAIL;
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}
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PRINTF("STATUS = LOW\n");
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return FPGA_SUCCESS;
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}
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/* Returns the state of CONF_DONE Pin */
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int fpga_done_fn (int cookie)
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{
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unsigned long reg;
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reg = in32(GPIO0_IR);
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if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) {
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PRINTF("CONF_DON = HIGH\n");
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return FPGA_FAIL;
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}
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PRINTF("CONF_DON = LOW\n");
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return FPGA_SUCCESS;
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}
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/* writes the complete buffer to the FPGA
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writing the complete buffer in one function is much faster,
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then calling it for every bit */
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int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
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{
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size_t bytecount = 0;
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unsigned char *data = (unsigned char *) buf;
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unsigned char val=0;
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int i;
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int len_40 = len / 40;
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while (bytecount < len) {
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val = data[bytecount++];
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i = 8;
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do {
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if (val & 0x01) {
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FPGA_WRITE_1;
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} else {
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FPGA_WRITE_0;
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}
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val >>= 1;
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i --;
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} while (i > 0);
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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if (bytecount % len_40 == 0) {
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putc ('.'); /* let them know we are alive */
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#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
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if (ctrlc ())
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return FPGA_FAIL;
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#endif
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}
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#endif
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}
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return FPGA_SUCCESS;
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}
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/* called, when programming is aborted */
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int fpga_abort_fn (int cookie)
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{
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SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR));
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return FPGA_SUCCESS;
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}
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/* called, when programming was succesful */
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int fpga_post_fn (int cookie)
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{
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return fpga_abort_fn (cookie);
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}
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/* Note that these are pointers to code that is in Flash. They will be
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* relocated at runtime.
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*/
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Altera_CYC2_Passive_Serial_fns fpga_fns = {
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fpga_pre_fn,
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fpga_config_fn,
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fpga_status_fn,
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fpga_done_fn,
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fpga_write_fn,
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fpga_abort_fn,
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fpga_post_fn
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};
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Altera_desc fpga[CONFIG_FPGA_COUNT] = {
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{Altera_CYC2,
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passive_serial,
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Altera_EP2C35_SIZE,
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(void *) &fpga_fns,
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NULL,
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0}
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};
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/*
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* Initialize the fpga. Return 1 on success, 0 on failure.
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*/
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int alpr_fpga_init (void)
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{
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int i;
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PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
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fpga_init (gd->reloc_off);
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for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
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PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
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fpga_add (fpga_altera, &fpga[i]);
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}
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return 1;
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}
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#endif
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