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u-boot/arch/riscv/cpu/jh7110
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Minda Chen eca2d41c68 riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE 
Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:01 +08:00
..
cpu.c riscv: cpu: jh7110: Add support for jh7110 SoC 2023-04-20 16:08:44 +08:00
dram.c riscv: cpu: jh7110: Add support for jh7110 SoC 2023-04-20 16:08:44 +08:00
Kconfig riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE 2023-08-10 10:58:01 +08:00
Makefile riscv: cpu: jh7110: Add support for jh7110 SoC 2023-04-20 16:08:44 +08:00
spl.c ram: starfive: Read memory size information from EEPROM 2023-07-12 13:21:40 +08:00