u-boot/arch/powerpc/cpu/mpc85xx/mp.h
York Sun ffd06e0231 powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:32 -05:00

21 lines
518 B
C

#ifndef __MPC85XX_MP_H_
#define __MPC85XX_MP_H_
#include <asm/mp.h>
phys_addr_t get_spin_phys_addr(void);
u32 get_my_id(void);
int hold_cores_in_reset(int verbose);
#define BOOT_ENTRY_ADDR_UPPER 0
#define BOOT_ENTRY_ADDR_LOWER 1
#define BOOT_ENTRY_R3_UPPER 2
#define BOOT_ENTRY_R3_LOWER 3
#define BOOT_ENTRY_RESV 4
#define BOOT_ENTRY_PIR 5
#define BOOT_ENTRY_R6_UPPER 6
#define BOOT_ENTRY_R6_LOWER 7
#define NUM_BOOT_ENTRY 16 /* pad to 64 bytes */
#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32))
#endif