mirror of
https://github.com/AsahiLinux/u-boot
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ec8242cceb
Add the node for PCIe 2x1l 2 device together with the corresponding combphy. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> [eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor adaptations] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> [jonas@kwiboo.se: adapt to kernel node] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
244 lines
6 KiB
Text
244 lines
6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
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*/
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#include "rockchip-u-boot.dtsi"
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#include <dt-bindings/phy/phy.h>
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/ {
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dmc {
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compatible = "rockchip,rk3588-dmc";
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bootph-all;
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status = "okay";
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};
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usb_host0_ehci: usb@fc800000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfc800000 0x0 0x40000>;
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interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
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clock-names = "usbhost", "arbiter";
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power-domains = <&power RK3588_PD_USB>;
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status = "disabled";
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};
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usb_host0_ohci: usb@fc840000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfc840000 0x0 0x40000>;
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interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
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clock-names = "usbhost", "arbiter";
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power-domains = <&power RK3588_PD_USB>;
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status = "disabled";
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};
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usb_host1_ehci: usb@fc880000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfc880000 0x0 0x40000>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
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clock-names = "usbhost", "arbiter";
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power-domains = <&power RK3588_PD_USB>;
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status = "disabled";
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};
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usb_host1_ohci: usb@fc8c0000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfc8c0000 0x0 0x40000>;
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interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
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clock-names = "usbhost", "arbiter";
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power-domains = <&power RK3588_PD_USB>;
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status = "disabled";
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};
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pmu1_grf: syscon@fd58a000 {
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bootph-all;
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compatible = "rockchip,rk3588-pmu1-grf", "syscon";
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reg = <0x0 0xfd58a000 0x0 0x2000>;
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};
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pipe_phy0_grf: syscon@fd5bc000 {
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compatible = "rockchip,pipe-phy-grf", "syscon";
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reg = <0x0 0xfd5bc000 0x0 0x100>;
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};
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usb2phy2_grf: syscon@fd5d8000 {
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compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
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"simple-mfd";
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reg = <0x0 0xfd5d8000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy2: usb2-phy@8000 {
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compatible = "rockchip,rk3588-usb2phy";
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reg = <0x8000 0x10>;
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interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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status = "disabled";
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u2phy2_host: host-port {
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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usb2phy3_grf: syscon@fd5dc000 {
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compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
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"simple-mfd";
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reg = <0x0 0xfd5dc000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy3: usb2-phy@c000 {
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compatible = "rockchip,rk3588-usb2phy";
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reg = <0xc000 0x10>;
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interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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status = "disabled";
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u2phy3_host: host-port {
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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pcie2x1l2: pcie@fe190000 {
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compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x40 0x4f>;
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clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
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<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
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<&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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device_type = "pci";
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interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
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<0 0 0 2 &pcie2x1l2_intc 1>,
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<0 0 0 3 &pcie2x1l2_intc 2>,
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<0 0 0 4 &pcie2x1l2_intc 3>;
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linux,pci-domain = <4>;
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num-ib-windows = <8>;
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num-ob-windows = <8>;
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num-viewport = <4>;
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max-link-speed = <2>;
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msi-map = <0x4000 &gic 0x4000 0x1000>;
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num-lanes = <1>;
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phys = <&combphy0_ps PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
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<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
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<0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
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reg = <0xa 0x41000000 0x0 0x00400000>,
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<0x0 0xfe190000 0x0 0x00010000>,
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<0x0 0xf4000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
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reset-names = "pcie", "periph";
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rockchip,pipe-grf = <&php_grf>;
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status = "disabled";
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pcie2x1l2_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
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};
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};
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otp: nvmem@fecc0000 {
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compatible = "rockchip,rk3588-otp";
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reg = <0x0 0xfecc0000 0x0 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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cpu_id: id@7 {
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reg = <0x07 0x10>;
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};
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};
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rng: rng@fe378000 {
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compatible = "rockchip,trngv1";
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reg = <0x0 0xfe378000 0x0 0x200>;
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status = "disabled";
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};
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combphy0_ps: phy@fee00000 {
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compatible = "rockchip,rk3588-naneng-combphy";
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reg = <0x0 0xfee00000 0x0 0x100>;
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#phy-cells = <1>;
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clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
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<&cru PCLK_PHP_ROOT>;
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clock-names = "refclk", "apbclk", "phpclk";
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assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
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assigned-clock-rates = <100000000>;
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resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
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reset-names = "combphy-apb", "combphy";
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rockchip,pipe-grf = <&php_grf>;
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rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
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status = "disabled";
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};
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};
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&xin24m {
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bootph-all;
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status = "okay";
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};
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&cru {
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bootph-pre-ram;
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status = "okay";
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};
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&sys_grf {
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bootph-pre-ram;
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status = "okay";
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};
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&scmi {
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bootph-pre-ram;
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};
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&scmi_clk {
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bootph-pre-ram;
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};
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&sdmmc {
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bootph-pre-ram;
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u-boot,spl-fifo-mode;
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};
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&sdhci {
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bootph-pre-ram;
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u-boot,spl-fifo-mode;
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};
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&uart2 {
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clock-frequency = <24000000>;
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bootph-pre-ram;
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status = "okay";
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};
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&ioc {
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bootph-pre-ram;
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};
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