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https://github.com/AsahiLinux/u-boot
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de3db25231
Add register address and relevant bitmasks and shifts. Allow reading these information: - device identification - number of cores (part of device identification) - features (currently: PRU / no PRU) - security - functional safety - speed grade - temperature grade - package Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Andrew Davis <afd@ti.com>
90 lines
2.9 KiB
C
90 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: AM62 SoC definitions, structures etc.
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*
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* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
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* Suman Anna <s-anna@ti.com>
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*/
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#ifndef __ASM_ARCH_AM62_HARDWARE_H
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#define __ASM_ARCH_AM62_HARDWARE_H
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#include <config.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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#define PADCFG_MMR0_BASE 0x04080000
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#define PADCFG_MMR1_BASE 0x000f0000
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#define CTRL_MMR0_BASE 0x00100000
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#define MCU_CTRL_MMR0_BASE 0x04500000
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#define WKUP_CTRL_MMR0_BASE 0x43000000
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#define CTRLMMR_WKUP_JTAG_DEVICE_ID (WKUP_CTRL_MMR0_BASE + 0x18)
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#define JTAG_DEV_ID_MASK GENMASK(31, 18)
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#define JTAG_DEV_ID_SHIFT 18
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#define JTAG_DEV_CORE_NR_MASK GENMASK(21, 19)
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#define JTAG_DEV_CORE_NR_SHIFT 19
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#define JTAG_DEV_GPU_MASK BIT(18)
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#define JTAG_DEV_GPU_SHIFT 18
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#define JTAG_DEV_FEATURES_MASK GENMASK(17, 13)
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#define JTAG_DEV_FEATURES_SHIFT 13
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#define JTAG_DEV_SECURITY_MASK BIT(12)
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#define JTAG_DEV_SECURITY_SHIFT 12
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#define JTAG_DEV_SAFETY_MASK BIT(11)
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#define JTAG_DEV_SAFETY_SHIFT 11
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#define JTAG_DEV_SPEED_MASK GENMASK(10, 6)
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#define JTAG_DEV_SPEED_SHIFT 6
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#define JTAG_DEV_TEMP_MASK GENMASK(5, 3)
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#define JTAG_DEV_TEMP_SHIFT 3
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#define JTAG_DEV_PKG_MASK GENMASK(2, 0)
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#define JTAG_DEV_PKG_SHIFT 0
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#define JTAG_DEV_FEATURE_NO_PRU 0x4
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#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10)
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13)
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
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#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK (~BIT(17))
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/* Primary Bootmode MMC Config macros */
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#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
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#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
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#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1
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#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0
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/* Primary Bootmode USB Config macros */
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#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
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#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
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/* Backup Bootmode USB Config macros */
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#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
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#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
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#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c)
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#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
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#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
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#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
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#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
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#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0
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#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
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#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
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static const u32 put_device_ids[] = {};
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static const u32 put_core_ids[] = {};
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#endif
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#endif /* __ASM_ARCH_AM62_HARDWARE_H */
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