mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-26 13:03:40 +00:00
da880bf7c1
After "spi: spi_flash_probe_bus_cs() rely on DT for spi speed and mode" series flash speed and mode wasn't passed to driver anymore, which resulted in: Loading Environment from SPIFlash... tegra20_sflash spi@7000c380: Invalid chip select 0:0 (err=-19) *** Warning - spi_flash_probe_bus_cs() failed, using default environment Fix it by syncing SPI node of affected device dts with Linux kernel dts. The changed SPI bus frequency doesn't influence stability of read/write operations. Ref: https://patchwork.ozlabs.org/project/uboot/cover/20220518064648.1843664-1-patrice.chotard@foss.st.com Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
141 lines
2.7 KiB
Text
141 lines
2.7 KiB
Text
/dts-v1/;
|
|
|
|
#include "tegra20.dtsi"
|
|
|
|
/ {
|
|
model = "Compulab TrimSlice board";
|
|
compatible = "compulab,trimslice", "nvidia,tegra20";
|
|
|
|
chosen {
|
|
stdout-path = &uarta;
|
|
};
|
|
|
|
aliases {
|
|
usb0 = "/usb@c5000000";
|
|
mmc0 = "/sdhci@c8000600";
|
|
mmc1 = "/sdhci@c8000000";
|
|
spi0 = "/spi@7000c380";
|
|
};
|
|
|
|
memory {
|
|
reg = <0x00000000 0x40000000>;
|
|
};
|
|
|
|
serial@70006000 {
|
|
clock-frequency = <216000000>;
|
|
};
|
|
|
|
spi@7000c380 {
|
|
status = "okay";
|
|
spi-max-frequency = <48000000>;
|
|
|
|
flash@0 {
|
|
compatible = "winbond,w25q80bl", "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <48000000>;
|
|
};
|
|
};
|
|
|
|
pcie@80003000 {
|
|
status = "okay";
|
|
|
|
avdd-pex-supply = <&pci_vdd_reg>;
|
|
vdd-pex-supply = <&pci_vdd_reg>;
|
|
avdd-pex-pll-supply = <&pci_vdd_reg>;
|
|
avdd-plle-supply = <&pci_vdd_reg>;
|
|
vddio-pex-clk-supply = <&pci_clk_reg>;
|
|
|
|
pci@1,0 {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
usb@c5000000 {
|
|
status = "okay";
|
|
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
sdhci@c8000000 {
|
|
status = "okay";
|
|
bus-width = <4>;
|
|
};
|
|
|
|
sdhci@c8000600 {
|
|
status = "okay";
|
|
cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
|
|
wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
|
|
bus-width = <4>;
|
|
};
|
|
|
|
clocks {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
clk32k_in: clock@0 {
|
|
compatible = "fixed-clock";
|
|
reg=<0>;
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
};
|
|
|
|
regulators {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
hdmi_vdd_reg: regulator@0 {
|
|
compatible = "regulator-fixed";
|
|
reg = <0>;
|
|
regulator-name = "avdd_hdmi";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
hdmi_pll_reg: regulator@1 {
|
|
compatible = "regulator-fixed";
|
|
reg = <1>;
|
|
regulator-name = "avdd_hdmi_pll";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vbus_reg: regulator@2 {
|
|
compatible = "regulator-fixed";
|
|
reg = <2>;
|
|
regulator-name = "usb1_vbus";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
enable-active-high;
|
|
gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
pci_clk_reg: regulator@3 {
|
|
compatible = "regulator-fixed";
|
|
reg = <3>;
|
|
regulator-name = "pci_clk";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
pci_vdd_reg: regulator@4 {
|
|
compatible = "regulator-fixed";
|
|
reg = <4>;
|
|
regulator-name = "pci_vdd";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
&uarta {
|
|
status = "okay";
|
|
};
|