mirror of
https://github.com/AsahiLinux/u-boot
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fb2bdc4efc
i.MX93 11x11 EVK fails to boot: U-Boot SPL 2023.10-00558-g65b9b3462bec-dirty (Oct 03 2023 - 17:40:10 +0200) SOC: 0xa0009300 LC: 0x40010 M33 prepare ok Normal Boot Trying to boot from BOOTROM Boot Stage: Primary boot image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x44400 by ROM_API NOTICE: BL31: v2.8(release):android-13.0.0_2.0.0-0-ge4b2dbfa52f5 NOTICE: BL31: Built : 17:52:46, Sep 28 2023 That's because commit9e644284ab("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation"): "[This] changes behavior of what nodes are bound in the U-Boot proper pre-relocation phase. Change to bootph-all or add bootph-some-ram prop to restore prior behavior." Fix this by adding bootph-some-ram prop as suggested by the commit above. Fixes:9e644284ab("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation") Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
171 lines
2.1 KiB
Text
171 lines
2.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 NXP
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*/
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog3>;
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bootph-pre-ram;
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bootph-some-ram;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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&{/soc@0} {
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bootph-all;
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bootph-pre-ram;
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};
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&aips1 {
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bootph-pre-ram;
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bootph-all;
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};
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&aips2 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&aips3 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&iomuxc {
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bootph-pre-ram;
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bootph-some-ram;
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};
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®_usdhc2_vmmc {
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u-boot,off-on-delay-us = <20000>;
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl_reg_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_uart1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl_usdhc2_gpio {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&gpio1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&gpio3 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&lpuart1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&usdhc1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&usdhc2 {
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bootph-pre-ram;
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bootph-some-ram;
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fsl,signal-voltage-switch-extra-delay-ms = <8>;
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};
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&lpi2c2 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl_lpi2c2 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&fec {
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phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <15>;
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phy-reset-post-delay = <100>;
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};
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&eqos {
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compatible = "fsl,imx-eqos";
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};
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ðphy1 {
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reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
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reset-assert-us = <15000>;
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reset-deassert-us = <100000>;
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};
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&s4muap {
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bootph-pre-ram;
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bootph-some-ram;
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status = "okay";
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};
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&clk {
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bootph-all;
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bootph-pre-ram;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-rates;
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/delete-property/ assigned-clock-parents;
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};
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&osc_32k {
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bootph-all;
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bootph-pre-ram;
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};
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&osc_24m {
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bootph-all;
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bootph-pre-ram;
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};
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&clk_ext1 {
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bootph-all;
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bootph-pre-ram;
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};
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