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The memory map for the RZ/G2L family differs from that of previous R-Car
Gen3/Gen4 SoCs.
A high level memory map can be seen in figure 5.2 (section 5.2.1) of the
RZ/G2L data sheet rev 1.30 published May 12, 2023. A summary is included
here (note that this is a 34-bit address space):
* 0x0_0000_0000 - 0x0_0002_FFFF SRAM area
* 0x0_0003_0000 - 0x0_0FFF_FFFF Reserved area
* 0x0_1000_0000 - 0x0_1FFF_FFFF I/O register area
* 0x0_2000_0000 - 0x0_2FFF_FFFF SPI Multi area
* 0x0_3000_0000 - 0x0_3FFF_FFFF Reserved area
* 0x0_4000_0000 - 0x1_3FFF_FFFF DDR area (4 GiB)
* 0x1_4000_0000 - 0x3_FFFF_FFFF Reserved area
Within the DDR area, the first 128 MiB are reserved by TrustedFirmware.
The region from 0x43F00000 to 0x47DFFFFF inclusive is protected for use
in TrustedFirmware/OP-TEE, but all other memory is included in the
memory map. This reservation is the same as used in R-Car
Gen3/Gen4 and RZ/G2{H,M,N,E} SoCs.
DRAM information is initialised based on the data in the fdt.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
127 lines
2.9 KiB
C
127 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Renesas RZ/G2L family memory map tables
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*
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* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include <common.h>
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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#include <cpu_func.h>
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#define RZG2L_NR_REGIONS 16
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/*
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* RZ/G2L supports up to 4 GiB RAM starting at 0x40000000, of
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* which the first 128 MiB is reserved by TF-A.
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*/
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static struct mm_region rzg2l_mem_map[RZG2L_NR_REGIONS] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x03F00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x47E00000UL,
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.phys = 0x47E00000UL,
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.size = 0xF8200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rzg2l_mem_map;
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DECLARE_GLOBAL_DATA_PTR;
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#define debug_memmap(i, map) \
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debug("memmap %d: virt 0x%llx -> phys 0x%llx, size=0x%llx, attrs=0x%llx\n", \
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i, map[i].virt, map[i].phys, map[i].size, map[i].attrs)
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void enable_caches(void)
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{
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unsigned int bank, i = 0;
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u64 start, size;
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/* Create map for register access */
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rzg2l_mem_map[i].virt = 0x0ULL;
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rzg2l_mem_map[i].phys = 0x0ULL;
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rzg2l_mem_map[i].size = 0x40000000ULL;
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rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN;
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debug_memmap(i, rzg2l_mem_map);
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i++;
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/* Generate entries for DRAM in 32bit address space */
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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start = gd->bd->bi_dram[bank].start;
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size = gd->bd->bi_dram[bank].size;
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/* Skip empty DRAM banks */
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if (!size)
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continue;
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/* Mark memory reserved by ATF as cacheable too. */
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if (start == 0x48000000) {
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/* Unmark protection area (0x43F00000 to 0x47DFFFFF) */
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rzg2l_mem_map[i].virt = 0x40000000ULL;
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rzg2l_mem_map[i].phys = 0x40000000ULL;
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rzg2l_mem_map[i].size = 0x03F00000ULL;
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rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE;
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debug_memmap(i, rzg2l_mem_map);
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i++;
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start = 0x47E00000ULL;
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size += 0x00200000ULL;
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}
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rzg2l_mem_map[i].virt = start;
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rzg2l_mem_map[i].phys = start;
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rzg2l_mem_map[i].size = size;
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rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE;
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debug_memmap(i, rzg2l_mem_map);
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i++;
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}
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/* Zero out the remaining regions. */
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for (; i < RZG2L_NR_REGIONS; i++) {
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rzg2l_mem_map[i].virt = 0;
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rzg2l_mem_map[i].phys = 0;
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rzg2l_mem_map[i].size = 0;
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rzg2l_mem_map[i].attrs = 0;
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debug_memmap(i, rzg2l_mem_map);
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}
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if (!icache_status())
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icache_enable();
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dcache_enable();
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}
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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