u-boot/arch/arm/dts/zynqmp-mini-qspi.dts
T Karthik Reddy d93fbac512 arm64: zynqmp: Fix zynqmp mini qspi max frequency
For zynqmp qspi, frequencies up to 40MHz will work irrespective
of feedback clock enabled or disabled. If we want higher than
40Mhz the feedback clock should be enabled.

With spi-max-frequency 108MHz it is not working when the feedback
clock is disabled. Change it to 40MHz so that it works irrespective
of feedback clock enabled or disabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00

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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP Mini Configuration
*
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
*/
/dts-v1/;
/ {
model = "ZynqMP MINI QSPI";
compatible = "xlnx,zynqmp";
#address-cells = <2>;
#size-cells = <1>;
aliases {
serial0 = &dcc;
spi0 = &qspi;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@fffc0000 {
device_type = "memory";
reg = <0x0 0xfffc0000 0x40000>;
};
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
u-boot,dm-pre-reloc;
};
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
qspi: spi@ff0f0000 {
compatible = "xlnx,zynqmp-qspi-1.0";
status = "disabled";
clock-names = "ref_clk", "pclk";
clocks = <&misc_clk &misc_clk>;
num-cs = <1>;
reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
#address-cells = <1>;
#size-cells = <0>;
};
misc_clk: misc_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
};
};
&qspi {
status = "okay";
flash0: flash@0 {
compatible = "n25q512a11", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>;
};
};
&dcc {
status = "okay";
};