u-boot/arch/arm/dts/socfpga_cyclone5_sr1500.dts
Simon Goldschmidt 7357c2cbc0 arm: socfpga: gen5: add reset & sdr node to SPL devicetrees
The SPL for socfpga gen5 currently takes all peripherals out of reset
unconditionally. To implement proper reset handling for peripherals,
the reset node has to be provided with the SPL dts.

In preparation to move the DDR driver to DM, the sdr node is required
in SPL, too.

This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon
files so that the reset manager and SDR driver correctly probe in SPL.
It centralizes these settings into a common file since in contrast to
boot-type specific nodes, "soc", "rst" and "sdr" are always needed.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17 22:20:16 +02:00

110 lines
1.6 KiB
Text

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
*/
#include "socfpga_cyclone5.dtsi"
#include "socfpga-common-u-boot.dtsi"
/ {
model = "SoCFPGA Cyclone V SR1500";
compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = "serial0:115200n8";
};
aliases {
/*
* This allows the ethaddr uboot environment variable
* contents to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
};
memory@0 {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&porta {
bank-name = "porta";
};
&portb {
bank-name = "portb";
};
&portc {
bank-name = "portc";
};
&i2c0 {
status = "okay";
speed-mode = <0>;
};
&i2c1 {
status = "okay";
speed-mode = <0>;
};
&mmc0 {
status = "okay";
bus-width = <8>;
u-boot,dm-pre-reloc;
};
&uart0 {
status = "okay";
u-boot,dm-pre-reloc;
};
&usb1 {
status = "okay";
};
&watchdog0 {
status = "okay";
};
&qspi {
status = "okay";
u-boot,dm-pre-reloc;
flash0: n25q00@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q00", "jedec,spi-nor";
reg = <0>; /* chip select */
spi-max-frequency = <100000000>;
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};