mirror of
https://github.com/AsahiLinux/u-boot
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77b11f7604
As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
171 lines
2.7 KiB
Text
171 lines
2.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP ls2080a RDB board device tree source for QSPI-boot
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*
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* Author: Priyanka Jain <priyanka.jain@nxp.com>
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*
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* Copyright 2017 NXP
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*/
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/dts-v1/;
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#include "fsl-ls2080a.dtsi"
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/ {
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model = "Freescale Layerscape 2080a RDB Board";
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compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
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aliases {
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spi0 = &qspi;
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spi1 = &dspi;
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};
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};
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&dpmac1 {
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status = "okay";
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phy-handle = <&mdio1_phy1>;
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phy-connection-type = "10gbase-r";
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};
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&dpmac2 {
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status = "okay";
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phy-handle = <&mdio1_phy2>;
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phy-connection-type = "10gbase-r";
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};
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&dpmac3 {
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status = "okay";
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phy-handle = <&mdio1_phy3>;
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phy-connection-type = "10gbase-r";
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};
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&dpmac4 {
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status = "okay";
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phy-handle = <&mdio1_phy4>;
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phy-connection-type = "10gbase-r";
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};
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&dpmac5 {
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status = "okay";
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phy-handle = <&mdio2_phy1>;
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phy-connection-type = "10gbase-r";
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};
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&dpmac6 {
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status = "okay";
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phy-handle = <&mdio2_phy2>;
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phy-connection-type = "10gbase-r";
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};
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&dpmac7 {
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status = "okay";
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phy-handle = <&mdio2_phy3>;
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phy-connection-type = "10gbase-r";
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};
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&dpmac8 {
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status = "okay";
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phy-handle = <&mdio2_phy4>;
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phy-connection-type = "10gbase-r";
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};
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&emdio1 {
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status = "okay";
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/* CS4340 PHYs */
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mdio1_phy1: emdio1_phy@1 {
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reg = <0x10>;
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};
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mdio1_phy2: emdio1_phy@2 {
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reg = <0x11>;
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};
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mdio1_phy3: emdio1_phy@3 {
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reg = <0x12>;
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};
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mdio1_phy4: emdio1_phy@4 {
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reg = <0x13>;
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};
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};
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&emdio2 {
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status = "okay";
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/* AQR405 PHYs */
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mdio2_phy1: emdio2_phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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mdio2_phy2: emdio2_phy@2 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x1>;
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};
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mdio2_phy3: emdio2_phy@3 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x2>;
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};
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mdio2_phy4: emdio2_phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x3>;
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};
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};
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&dspi {
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bus-num = <0>;
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status = "okay";
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dflash0: n25q512a {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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};
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&qspi {
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status = "okay";
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s25fs512s0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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s25fs512s1: flash@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <1>;
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};
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};
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&i2c0 {
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status = "okay";
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u-boot,dm-pre-reloc;
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pca9547@75 {
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compatible = "nxp,pca9547";
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reg = <0x75>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x01>;
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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};
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};
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};
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};
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&sata {
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status = "okay";
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};
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