u-boot/arch/arm/dts/armada-7040-db-nand.dts
Igal Liberman 2dbba24088 phy: marvell: rename comphy related definitions to COMPHY_XX
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX.
Those definition might be confused with MDIO PHY definitions.

This patch does the following changes:
 - PHY_TYPE_XX --> COMPHY_TYPE_XX
 - PHY_SPEED_XX --> COMPHY_SPEED_XX

This improves readability, no functional change.

Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29 07:45:24 +02:00

186 lines
3.1 KiB
Text

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016- 2021 Marvell International Ltd.
*/
/*
* Device Tree file for Marvell Armada 7040 Development board platform
* Boot device: NAND, 0xE (SW3)
*/
#include "armada-7040.dtsi"
/ {
model = "Marvell Armada 7040 DB board with NAND";
compatible = "marvell,armada7040-db-nand", "marvell,armada7040-db",
"marvell,armada7040", "marvell,armada-ap806-quad",
"marvell,armada-ap806";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
i2c0 = &cp0_i2c0;
spi0 = &cp0_spi1;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&ap_pinctl {
/* MPP Bus:
* SDIO [0-5]
* UART0 [11,19]
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
0x0 0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 >;
};
&uart0 {
status = "okay";
};
&cp0_pcie2 {
status = "okay";
};
&cp0_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
&cp0_pinctl {
/* MPP Bus:
* AUDIO [0-5]
* GBE [6-11]
* SS_PWDN [12]
* NF_RBn [13]
* GPIO [14]
* DEV_BUS [15-27]
* SATA1 [28]
* UART0 [29-30]
* MSS_VTT_EN [31]
* SMI [32,34]
* XSMI [35-36]
* I2C [37-38]
* RGMII1 [44-55]
* SD [56-61]
* GPIO [62]
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x9 0xa
0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0
0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1
0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
0xe 0xe 0x0>;
};
&cp0_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
status = "disabled";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <20000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x200000>;
};
partition@400000 {
label = "Filesystem";
reg = <0x200000 0xe00000>;
};
};
};
};
&cp0_sata0 {
status = "okay";
};
&cp0_usb3_0 {
status = "okay";
};
&cp0_usb3_1 {
status = "okay";
};
&cp0_comphy {
phy0 {
phy-type = <COMPHY_TYPE_SGMII2>;
phy-speed = <COMPHY_SPEED_3_125G>;
};
phy1 {
phy-type = <COMPHY_TYPE_USB3_HOST0>;
phy-speed = <COMPHY_SPEED_5G>;
};
phy2 {
phy-type = <COMPHY_TYPE_SGMII0>;
phy-speed = <COMPHY_SPEED_1_25G>;
};
phy3 {
phy-type = <COMPHY_TYPE_SATA1>;
phy-speed = <COMPHY_SPEED_5G>;
};
phy4 {
phy-type = <COMPHY_TYPE_USB3_HOST1>;
phy-speed = <COMPHY_SPEED_5G>;
};
phy5 {
phy-type = <COMPHY_TYPE_PEX2>;
phy-speed = <COMPHY_SPEED_5G>;
};
};
&cp0_nand {
status = "okay";
};
&cp0_utmi0 {
status = "okay";
};
&cp0_utmi1 {
status = "okay";
};
&ap_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
non-removable;
};
&cp0_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
non-removable;
};