mirror of
https://github.com/AsahiLinux/u-boot
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eb0ca6b5ec
The RK3399 SoC needs to know the voltage value provided by some regulators, which is done by setting relevant register bits. Configure these the way other RK3399 boards do, but with the same values as are set in the equivalent code in coreboot. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
108 lines
2.3 KiB
C
108 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 Google
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*/
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#include <common.h>
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#include <dm.h>
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#include <init.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/grf_rk3399.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/misc.h>
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#define GRF_IO_VSEL_BT656_SHIFT 0
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#define GRF_IO_VSEL_AUDIO_SHIFT 1
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#define PMUGRF_CON0_VSEL_SHIFT 8
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#define PMUGRF_CON0_VOL_SHIFT 9
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#ifdef CONFIG_SPL_BUILD
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/* provided to defeat compiler optimisation in board_init_f() */
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void gru_dummy_function(int i)
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{
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}
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int board_early_init_f(void)
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{
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# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
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int sum, i;
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/*
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* Add a delay and ensure that the compiler does not optimise this out.
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* This is needed since the power rails tail a while to turn on, and
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* we get garbage serial output otherwise.
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*/
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sum = 0;
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for (i = 0; i < 150000; i++)
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sum += i;
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gru_dummy_function(sum);
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#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
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return 0;
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}
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#endif
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#ifndef CONFIG_SPL_BUILD
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int board_early_init_r(void)
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{
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struct udevice *clk;
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int ret;
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/*
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* This init is done in SPL, but when chain-loading U-Boot SPL will
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* have been skipped. Allow the clock driver to check if it needs
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* setting up.
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*/
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(clk_rk3399), &clk);
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if (ret) {
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debug("%s: CLK init failed: %d\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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#endif
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static void setup_iodomain(void)
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{
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struct rk3399_grf_regs *grf =
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syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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struct rk3399_pmugrf_regs *pmugrf =
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syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
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/* BT656 and audio is in 1.8v domain */
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rk_setreg(&grf->io_vsel, (1 << GRF_IO_VSEL_BT656_SHIFT |
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1 << GRF_IO_VSEL_AUDIO_SHIFT));
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/*
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* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL
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* and explicitly configure that PMU1830_VOL to be 1.8V
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*/
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rk_setreg(&pmugrf->soc_con0, (1 << PMUGRF_CON0_VSEL_SHIFT |
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1 << PMUGRF_CON0_VOL_SHIFT));
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}
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int misc_init_r(void)
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{
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const u32 cpuid_offset = 0x7;
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const u32 cpuid_length = 0x10;
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u8 cpuid[cpuid_length];
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int ret;
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setup_iodomain();
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ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
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if (ret)
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return ret;
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ret = rockchip_cpuid_set(cpuid, cpuid_length);
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if (ret)
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return ret;
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ret = rockchip_setup_macaddr();
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return ret;
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}
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