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e392b923ed
We run 4 Arndale boards in our automated test framework, they have been running quite happily for quite some time using a Debian Wheezy userspace. However when upgrading to a Debian Jessie we started seeing frequent segmentation faults from gcc when building the kernel, to the extent that it is unable to successfully build the kernel twice in a row, and often fails on the first attempt. Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417 which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html and CPU Errata 773022 and 774769. This errata needs to be applied to all processors in an SMP system, meaning that the usual strategy of applying them in arch/arm/cpu/armv7/start.S is not appropriate (since that applies to the boot processor only). Instead we apply these errata in the secure monitor which is code that is traversed by all processors as they are brought up. The net affect on Arndale is that ACTLR changes from 0x40 to 0x2000042. I ran 17 kernel compile iterations overnight with no segfaults. Runtime testing was done on our v2014.10 based branch and forward ported (with only minimal and trivial contextual conflicts) to current master, where it has been build tested only. I suppose in theory these errata apply to any Exynos5250 based boards, but Arndale is the only one I have access to and I have therefore chosen to be conservative and only apply it there. Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list numerically sorted. Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
219 lines
5.4 KiB
ArmAsm
219 lines
5.4 KiB
ArmAsm
/*
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* code for switching cores into non-secure state and into HYP mode
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*
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* Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/gic.h>
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#include <asm/armv7.h>
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#include <asm/proc-armv/ptrace.h>
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.arch_extension sec
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.arch_extension virt
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.pushsection ._secure.text, "ax"
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.align 5
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/* the vector table for secure state and HYP mode */
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_monitor_vectors:
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.word 0 /* reset */
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.word 0 /* undef */
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adr pc, _secure_monitor
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.macro is_cpu_virt_capable tmp
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mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
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and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
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cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT)
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.endm
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/*
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* secure monitor handler
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* U-boot calls this "software interrupt" in start.S
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* This is executed on a "smc" instruction, we use a "smc #0" to switch
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* to non-secure state.
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* r0, r1, r2: passed to the callee
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* ip: target PC
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*/
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_secure_monitor:
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#ifdef CONFIG_ARMV7_PSCI
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ldr r5, =_psci_vectors @ Switch to the next monitor
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mcr p15, 0, r5, c12, c0, 1
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isb
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@ Obtain a secure stack, and configure the PSCI backend
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bl psci_arch_init
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#endif
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#ifdef CONFIG_ARM_ERRATA_773022
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mrc p15, 0, r5, c1, c0, 1
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orr r5, r5, #(1 << 1)
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mcr p15, 0, r5, c1, c0, 1
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isb
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#endif
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#ifdef CONFIG_ARM_ERRATA_774769
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mrc p15, 0, r5, c1, c0, 1
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orr r5, r5, #(1 << 25)
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mcr p15, 0, r5, c1, c0, 1
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isb
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#endif
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mrc p15, 0, r5, c1, c1, 0 @ read SCR
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bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
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orr r5, r5, #0x31 @ enable NS, AW, FW bits
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@ FIQ preserved for secure mode
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mov r6, #SVC_MODE @ default mode is SVC
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is_cpu_virt_capable r4
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#ifdef CONFIG_ARMV7_VIRT
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orreq r5, r5, #0x100 @ allow HVC instruction
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moveq r6, #HYP_MODE @ Enter the kernel as HYP
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#endif
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mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
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isb
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bne 1f
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@ Reset CNTVOFF to 0 before leaving monitor mode
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mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
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ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits
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movne r4, #0
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mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
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1:
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mov lr, ip
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mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
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tst lr, #1 @ Check for Thumb PC
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orrne ip, ip, #T_BIT @ Set T if Thumb
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orr ip, ip, r6 @ Slot target mode in
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msr spsr_cxfs, ip @ Set full SPSR
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movs pc, lr @ ERET to non-secure
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ENTRY(_do_nonsec_entry)
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mov ip, r0
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mov r0, r1
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mov r1, r2
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mov r2, r3
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smc #0
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ENDPROC(_do_nonsec_entry)
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.macro get_cbar_addr addr
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#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
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ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS
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#else
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mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
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bfc \addr, #0, #15 @ clear reserved bits
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#endif
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.endm
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.macro get_gicd_addr addr
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get_cbar_addr \addr
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add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset
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.endm
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.macro get_gicc_addr addr, tmp
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get_cbar_addr \addr
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is_cpu_virt_capable \tmp
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movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
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moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
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add \addr, \addr, \tmp
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.endm
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#ifndef CONFIG_ARMV7_PSCI
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/*
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* Secondary CPUs start here and call the code for the core specific parts
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* of the non-secure and HYP mode transition. The GIC distributor specific
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* code has already been executed by a C function before.
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* Then they go back to wfi and wait to be woken up by the kernel again.
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*/
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ENTRY(_smp_pen)
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cpsid i
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cpsid f
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bl _nonsec_init
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adr r0, _smp_pen @ do not use this address again
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b smp_waitloop @ wait for IPIs, board specific
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ENDPROC(_smp_pen)
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#endif
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/*
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* Switch a core to non-secure state.
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*
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* 1. initialize the GIC per-core interface
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* 2. allow coprocessor access in non-secure modes
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*
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* Called from smp_pen by secondary cores and directly by the BSP.
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* Do not assume that the stack is available and only use registers
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* r0-r3 and r12.
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*
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* PERIPHBASE is used to get the GIC address. This could be 40 bits long,
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* though, but we check this in C before calling this function.
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*/
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ENTRY(_nonsec_init)
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get_gicd_addr r3
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mvn r1, #0 @ all bits to 1
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str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts
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get_gicc_addr r3, r1
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mov r1, #3 @ Enable both groups
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str r1, [r3, #GICC_CTLR] @ and clear all other bits
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mov r1, #0xff
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str r1, [r3, #GICC_PMR] @ set priority mask register
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mrc p15, 0, r0, c1, c1, 2
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movw r1, #0x3fff
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movt r1, #0x0004
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orr r0, r0, r1
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mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec
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/* The CNTFRQ register of the generic timer needs to be
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* programmed in secure state. Some primary bootloaders / firmware
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* omit this, so if the frequency is provided in the configuration,
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* we do this here instead.
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* But first check if we have the generic timer.
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*/
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#ifdef CONFIG_TIMER_CLK_FREQ
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mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
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and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
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cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
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ldreq r1, =CONFIG_TIMER_CLK_FREQ
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mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
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#endif
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adr r1, _monitor_vectors
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mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
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isb
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mov r0, r3 @ return GICC address
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bx lr
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ENDPROC(_nonsec_init)
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#ifdef CONFIG_SMP_PEN_ADDR
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/* void __weak smp_waitloop(unsigned previous_address); */
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ENTRY(smp_waitloop)
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wfi
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ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
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ldr r1, [r1]
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#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
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rev r1, r1
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#endif
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cmp r0, r1 @ make sure we dont execute this code
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beq smp_waitloop @ again (due to a spurious wakeup)
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mov r0, r1
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b _do_nonsec_entry
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ENDPROC(smp_waitloop)
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.weak smp_waitloop
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#endif
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.popsection
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