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551265f0df
This patch enables the altera_spi and spi_flash drivers for the nios2-generic board. It allows access to the EPCS/SPI flash on the Altera EP1C20 board. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Tested-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
76 lines
2.4 KiB
C
76 lines
2.4 KiB
C
/*
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* (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This file is generated by sopc-create-config-files.
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*/
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#ifndef _CUSTOM_FPGA_H_
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#define _CUSTOM_FPGA_H_
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/* generated from std_1c20.sopc */
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/* cpu.data_master is a altera_nios2 */
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#define CONFIG_SYS_CLK_FREQ 50000000
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#define CONFIG_SYS_RESET_ADDR 0x00000000
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#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020
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#define CONFIG_SYS_ICACHE_SIZE 4096
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#define CONFIG_SYS_ICACHELINE_SIZE 32
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#define CONFIG_SYS_DCACHE_SIZE 2048
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#define CONFIG_SYS_DCACHELINE_SIZE 4
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/* sdram.s1 is a altera_avalon_new_sdram_controller */
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#define CONFIG_SYS_SDRAM_BASE 0x01000000
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#define CONFIG_SYS_SDRAM_SIZE 0x01000000
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/* uart1.s1 is a altera_avalon_uart */
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#define CONFIG_SYS_UART_BASE 0x82120840
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#define CONFIG_SYS_UART_FREQ 50000000
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#define CONFIG_SYS_UART_BAUD 115200
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/* lan91c111.s1 is a altera_avalon_lan91c111 */
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#define CONFIG_SMC91111_BASE 0x82110300
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#define CONFIG_SMC91111
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#define CONFIG_SMC_USE_32_BIT
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/* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */
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#define EPCS_CONTROLLER_REG_BASE 0x82100200
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#define CONFIG_SYS_ALTERA_SPI_LIST { EPCS_CONTROLLER_REG_BASE }
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#define CONFIG_ALTERA_SPI
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
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#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0
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/* led_pio.s1 is a altera_avalon_pio */
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#define LED_PIO_BASE 0x82120870
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/* high_res_timer.s1 is a altera_avalon_timer */
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#define CONFIG_SYS_TIMER_BASE 0x82120820
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#define CONFIG_SYS_TIMER_IRQ 3
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#define CONFIG_SYS_TIMER_FREQ 50000000
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/* ext_flash.s1 is a altera_avalon_cfi_flash */
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#define CONFIG_SYS_FLASH_BASE 0x80000000
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 1024
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/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */
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#define CONFIG_SYS_SRAM_BASE 0x02000000
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#define CONFIG_SYS_SRAM_SIZE 0x00100000
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/* sysid.control_slave is a altera_avalon_sysid */
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#define CONFIG_SYS_SYSID_BASE 0x821208b8
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#endif /* _CUSTOM_FPGA_H_ */
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