Lokesh Vutla ea8eff1fe0 arm: dra7xx: clock: Add the dplls data ... A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>		2013-03-11 11:06:11 -04:00
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boot-common.c	omap_hsmmc: add driver check for write protection	2013-03-08 16:41:13 -05:00
clocks-common.c	arm: dra7xx: clock: Add the dplls data	2013-03-11 11:06:11 -04:00
config.mk	arm: Remove additional config flags	2012-10-04 14:51:50 +02:00
emif-common.c	ARM: OMAP4+: Cleanup emif specific files	2013-03-11 11:06:10 -04:00
hwinit-common.c	ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup	2013-03-11 11:06:11 -04:00
lowlevel_init.S	am33xx: Fix fetching of mmc1 bootmode from bootrom for AM33XX	2012-10-01 10:02:15 -07:00
Makefile	OMAP: Tweak omap-common/Makefile since reset.S -> reset.c	2012-12-10 08:55:25 -07:00
mem-common.c	omap4: make omap4 code common for future reuse	2011-11-15 22:25:50 +01:00
reset.c	ARM: OMAP3+: Detect reset type	2012-07-07 14:07:34 +02:00
timer.c	arm: Move lastinc to arch_global_data	2013-02-01 15:07:50 -05:00
u-boot-spl.lds	common: Add .u_boot_list into all linker files	2012-10-22 08:29:42 -07:00
utils.c	omap4: calculate EMIF register values	2011-08-03 12:49:19 +02:00
vc.c	ARM: OMAP4+: Change the PRCM structure prototype common for all Socs	2013-03-11 11:06:09 -04:00