mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 20:54:31 +00:00
66ebea06f7
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, the rsb is also used to communicate with the pmic on the A80, and is documented in the A80 user manual. This commit adds support for this based on the rsb driver from the allwinner u-boot sources. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
240 lines
9 KiB
C
240 lines
9 KiB
C
/*
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* Sunxi A31 Power Management Unit register definition.
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*
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* (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
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* http://linux-sunxi.org
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Berg Xing <bergxing@allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_PRCM_H
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#define _SUNXI_PRCM_H
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#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)
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#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)
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#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)
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#define PRCM_CPUS_CFG_PRE_DIV(n) \
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__PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
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#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)
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#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)
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#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)
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#define PRCM_CPUS_CFG_POST_DIV(n) \
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__PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
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#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)
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#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)
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#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0
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#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1
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#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2
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#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3
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#define PRCM_CPUS_CFG_CLK_SRC_LOSC \
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__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)
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#define PRCM_CPUS_CFG_CLK_SRC_HOSC \
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__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)
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#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \
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__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)
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#define PRCM_CPUS_CFG_CLK_SRC_PDIV \
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__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)
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#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0)
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#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)
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#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)
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#define PRCM_APB0_RATIO_DIV(n) \
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__PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))
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#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)
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#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)
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#define PRCM_APB0_GATE_PIO (0x1 << 0)
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#define PRCM_APB0_GATE_IR (0x1 << 1)
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#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
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#define PRCM_APB0_GATE_P2WI (0x1 << 3) /* sun6i */
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#define PRCM_APB0_GATE_RSB (0x1 << 3) /* sun8i */
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#define PRCM_APB0_GATE_UART (0x1 << 4)
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#define PRCM_APB0_GATE_1WIRE (0x1 << 5)
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#define PRCM_APB0_GATE_I2C (0x1 << 6)
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#define PRCM_APB0_RESET_PIO (0x1 << 0)
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#define PRCM_APB0_RESET_IR (0x1 << 1)
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#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
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#define PRCM_APB0_RESET_P2WI (0x1 << 3)
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#define PRCM_APB0_RESET_UART (0x1 << 4)
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#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
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#define PRCM_APB0_RESET_I2C (0x1 << 6)
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#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)
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#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)
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#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)
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#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \
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__PRCM_PLL_CTRL_USB_CLK_SRC(0x3)
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#define __PRCM_PLL_CTRL_USB_CLK_0 0x0
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#define __PRCM_PLL_CTRL_USB_CLK_1 0x1
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#define __PRCM_PLL_CTRL_USB_CLK_2 0x2
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#define __PRCM_PLL_CTRL_USB_CLK_3 0x3
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#define PRCM_PLL_CTRL_USB_CLK_0 \
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__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0)
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#define PRCM_PLL_CTRL_USB_CLK_1 \
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__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1)
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#define PRCM_PLL_CTRL_USB_CLK_2 \
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__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2)
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#define PRCM_PLL_CTRL_USB_CLK_3 \
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__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3)
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#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12)
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#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \
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__PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3)
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#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \
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__PRCM_PLL_CTRL_INT_PLL_IN_SEL(n)
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#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20)
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#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \
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__PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3)
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#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0
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#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1
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#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2
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#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3
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#define PRCM_PLL_CTRL_HOSC_CLK_0 \
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__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0)
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#define PRCM_PLL_CTRL_HOSC_CLK_1 \
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__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1)
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#define PRCM_PLL_CTRL_HOSC_CLK_2 \
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__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2)
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#define PRCM_PLL_CTRL_HOSC_CLK_3 \
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__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3)
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#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24)
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#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0)
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#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1)
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#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2)
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#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3)
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#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */
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#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16)
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#define PRCM_PLL_CTRL_LDO_OUT_MASK \
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__PRCM_PLL_CTRL_LDO_OUT(0x7)
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/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
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#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
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__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
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#define PRCM_PLL_CTRL_LDO_OUT_H(n) \
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__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
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#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
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__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
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#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
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__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
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#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
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#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)
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#define PRCM_CLK_1WIRE_GATE (0x1 << 31)
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#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0)
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#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf)
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#define __PRCM_CLK_MOD0_M_X(n) (n - 1)
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#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n))
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#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8)
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#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7)
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#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16)
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#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3)
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#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1)
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#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n))
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#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20)
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#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7)
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#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24)
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#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7)
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#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31)
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#define PRCM_APB0_RESET_PIO (0x1 << 0)
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#define PRCM_APB0_RESET_IR (0x1 << 1)
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#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
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#define PRCM_APB0_RESET_P2WI (0x1 << 3)
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#define PRCM_APB0_RESET_UART (0x1 << 4)
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#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
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#define PRCM_APB0_RESET_I2C (0x1 << 6)
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#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8)
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#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7)
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#define __PRCM_CLK_OUTD_M_X() ((n) - 1)
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#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n))
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#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20)
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#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7)
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#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1)
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#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n)
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#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24)
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#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3)
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#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0
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#define __PRCM_CLK_OUTD_SRC_LOSC 0x1
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#define __PRCM_CLK_OUTD_SRC_HOSC 0x2
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#define __PRCM_CLK_OUTD_SRC_ERR 0x3
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#define PRCM_CLK_OUTD_SRC_LOSC2 \
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#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2)
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#define PRCM_CLK_OUTD_SRC_LOSC \
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#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC)
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#define PRCM_CLK_OUTD_SRC_HOSC \
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#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC)
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#define PRCM_CLK_OUTD_SRC_ERR \
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#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR)
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#define PRCM_CLK_OUTD_EN (0x1 << 31)
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#define PRCM_CPU0_PWROFF (0x1 << 0)
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#define PRCM_CPU1_PWROFF (0x1 << 1)
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#define PRCM_CPU2_PWROFF (0x1 << 2)
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#define PRCM_CPU3_PWROFF (0x1 << 3)
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#define PRCM_CPU_ALL_PWROFF (0xf << 0)
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#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0)
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#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1)
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#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2)
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#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3)
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#define PRCM_VDD_GPU_PWROFF (0x1 << 0)
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#define PRCM_VDD_SYS_RESET (0x1 << 0)
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#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0)
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#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff)
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#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0)
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#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff)
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#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)
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#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
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#ifndef __ASSEMBLY__
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struct sunxi_prcm_reg {
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u32 cpus_cfg; /* 0x000 */
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u8 res0[0x8]; /* 0x004 */
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u32 apb0_ratio; /* 0x00c */
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u32 cpu0_cfg; /* 0x010 */
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u32 cpu1_cfg; /* 0x014 */
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u32 cpu2_cfg; /* 0x018 */
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u32 cpu3_cfg; /* 0x01c */
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u8 res1[0x8]; /* 0x020 */
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u32 apb0_gate; /* 0x028 */
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u8 res2[0x14]; /* 0x02c */
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u32 pll_ctrl0; /* 0x040 */
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u32 pll_ctrl1; /* 0x044 */
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u8 res3[0x8]; /* 0x048 */
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u32 clk_1wire; /* 0x050 */
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u32 clk_ir; /* 0x054 */
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u8 res4[0x58]; /* 0x058 */
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u32 apb0_reset; /* 0x0b0 */
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u8 res5[0x3c]; /* 0x0b4 */
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u32 clk_outd; /* 0x0f0 */
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u8 res6[0xc]; /* 0x0f4 */
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u32 cpu_pwroff; /* 0x100 */
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u8 res7[0xc]; /* 0x104 */
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u32 vdd_sys_pwroff; /* 0x110 */
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u8 res8[0x4]; /* 0x114 */
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u32 gpu_pwroff; /* 0x118 */
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u8 res9[0x4]; /* 0x11c */
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u32 vdd_pwr_reset; /* 0x120 */
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u8 res10[0x20]; /* 0x124 */
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u32 cpu1_pwr_clamp; /* 0x144 */
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u32 cpu2_pwr_clamp; /* 0x148 */
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u32 cpu3_pwr_clamp; /* 0x14c */
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u8 res11[0x30]; /* 0x150 */
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u32 dram_pwr; /* 0x180 */
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u8 res12[0xc]; /* 0x184 */
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u32 dram_tst; /* 0x190 */
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};
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void prcm_apb0_enable(u32 flags);
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#endif /* __ASSEMBLY__ */
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#endif /* _PRCM_H */
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