mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
f8bbb4dad0
The eXMeritus HWW-1U-1A unit is a DO-160-certified 13lb 1U chassis
with 3 independent TEMPEST zones. Two independent P2020 computers may
be found inside each zone. Complete hardware support is included.
High-level hardware overview:
* DO-160 certified for passenger aircraft (noncritical)
* TEMPEST ceritified for RED/BLACK separation
* 3 zones per chassis, 2 computers per zone (total of 6)
* Dual-core 1.066GHz P2020 per computer
* One 2GB DDR2 SO-RDIMM module per computer (upgradable to 4GB)
* Removable 80GB or 160GB Intel X18-M SSD per computer
* Front-accessible dual-port E1000E per computer
* Front-accessible serial console per computer
* Front-accessible USB port per computer
* Internal Gigabit crossover within each TEMPEST zone
* Internal unidirectional fiber links across TEMPEST zones
* Battery-backed DS1339 I2C RTC on each CPU.
Combined, each 13lb 1U chassis contains 12GB RAM, 12 cores @ 1.066GHz,
12 front-accessible Gigabit Ethernet ports and 960GB of solid-state
storage with a total power consumption of ~200W.
Additional notes:
* SPD detection is only known to work with the DO-160-certified DIMMs
* CPU reset is a little quirky due to hardware misfeature. Proper
support for the hardware reset mechanism has been left for a later
patch series to address.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
69 lines
2.7 KiB
C
69 lines
2.7 KiB
C
/*
|
|
* Copyright 2010 eXMeritus, A Boeing Company
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#include <asm/mpc85xx_gpio.h>
|
|
|
|
/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */
|
|
#define GPIO_CPU_ID (1UL << (31 - 8))
|
|
#define GPIO_BLUE_LED (1UL << (31 - 9))
|
|
#define GPIO_DIMM_RESET (1UL << (31 - 10))
|
|
#define GPIO_USB_RESET (1UL << (31 - 11))
|
|
#define GPIO_UNUSED_12 (1UL << (31 - 12))
|
|
#define GPIO_GETH0_RESET (1UL << (31 - 13))
|
|
#define GPIO_RS422_RE (1UL << (31 - 14))
|
|
#define GPIO_RS422_DE (1UL << (31 - 15))
|
|
#define IRQ_I2CINT (1UL << (31 - 20))
|
|
#define IRQ_FANINT (1UL << (31 - 21))
|
|
#define IRQ_DIMM_EVENT (1UL << (31 - 22))
|
|
|
|
#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET)
|
|
|
|
/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
|
|
#define GPIO_CPUA_UNUSED_0 (1UL << (31 - 0))
|
|
#define GPIO_CPUA_CPU_READY (1UL << (31 - 1))
|
|
#define GPIO_CPUA_DEBUG_LED2 (1UL << (31 - 2))
|
|
#define GPIO_CPUA_DEBUG_LED1 (1UL << (31 - 3))
|
|
#define GPIO_CPUA_TDIS2B (1UL << (31 - 4)) /* MAC 2 TX B */
|
|
#define GPIO_CPUA_TDIS2A (1UL << (31 - 5)) /* MAC 2 TX A */
|
|
#define GPIO_CPUA_TDIS1B (1UL << (31 - 6)) /* MAC 1 TX B */
|
|
#define GPIO_CPUA_TDIS1A (1UL << (31 - 7)) /* MAC 1 TX A */
|
|
#define IRQ_CPUA_UNUSED_0 (1UL << (31 - 16))
|
|
#define IRQ_CPUA_UNUSED_1 (1UL << (31 - 17))
|
|
#define IRQ_CPUA_UNUSED_2 (1UL << (31 - 18))
|
|
#define IRQ_CPUA_UNUSED_3 (1UL << (31 - 19))
|
|
|
|
/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
|
|
#define GPIO_CPUB_RMUX_SEL1B (1UL << (31 - 0))
|
|
#define GPIO_CPUB_RMUX_SEL0B (1UL << (31 - 1))
|
|
#define GPIO_CPUB_RMUX_SEL1A (1UL << (31 - 2))
|
|
#define GPIO_CPUB_RMUX_SEL0A (1UL << (31 - 3))
|
|
#define GPIO_CPUB_UNUSED_4 (1UL << (31 - 4))
|
|
#define GPIO_CPUB_CPU_READY (1UL << (31 - 5))
|
|
#define GPIO_CPUB_DEBUG_LED2 (1UL << (31 - 6))
|
|
#define GPIO_CPUB_DEBUG_LED1 (1UL << (31 - 7))
|
|
#define IRQ_CPUB_SD_1A (1UL << (31 - 16))
|
|
#define IRQ_CPUB_SD_2B (1UL << (31 - 17))
|
|
#define IRQ_CPUB_SD_2A (1UL << (31 - 18))
|
|
#define IRQ_CPUB_SD_1B (1UL << (31 - 19))
|
|
|
|
/* If it isn't CPU A then it's CPU B */
|
|
static inline unsigned int hww1u1a_is_cpu_a(void)
|
|
{
|
|
return !mpc85xx_gpio_get(GPIO_CPU_ID);
|
|
}
|