mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-14 07:13:03 +00:00
0914011310
We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
167 lines
3.5 KiB
C
167 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <command.h>
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#include <dm.h>
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#include <env.h>
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#include <clk.h>
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#include <init.h>
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#include <malloc.h>
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#include <asm/armv7.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/grf_rk3288.h>
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#include <asm/arch-rockchip/pmu_rk3288.h>
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#include <asm/arch-rockchip/qos_rk3288.h>
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#include <asm/arch-rockchip/sdram.h>
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#include <linux/err.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GRF_BASE 0xff770000
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
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[BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
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};
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#ifdef CONFIG_SPL_BUILD
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static void configure_l2ctlr(void)
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{
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u32 l2ctlr;
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l2ctlr = read_l2ctlr();
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l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
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/*
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* Data RAM write latency: 2 cycles
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* Data RAM read latency: 2 cycles
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* Data RAM setup latency: 1 cycle
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* Tag RAM write latency: 1 cycle
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* Tag RAM read latency: 1 cycle
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* Tag RAM setup latency: 1 cycle
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*/
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l2ctlr |= (1 << 3 | 1 << 0);
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write_l2ctlr(l2ctlr);
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}
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#endif
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int rk3288_qos_init(void)
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{
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int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
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/* set vop qos to higher priority */
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writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
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writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
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if (!fdt_node_check_compatible(gd->fdt_blob, 0,
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"rockchip,rk3288-tinker")) {
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/* set isp qos to higher priority */
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writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
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writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
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writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
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}
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return 0;
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}
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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configure_l2ctlr();
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#else
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/* We do some SoC one time setting here. */
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struct rk3288_grf * const grf = (void *)GRF_BASE;
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/* Use rkpwm by default */
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rk_setreg(&grf->soc_con2, 1 << 0);
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/*
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* Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
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* cleared
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*/
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rk_clrreg(&grf->soc_con0, 1 << 12);
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rk3288_qos_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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/* Enable early UART on the RK3288 */
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struct rk3288_grf * const grf = (void *)GRF_BASE;
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rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
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GPIO7C6_MASK << GPIO7C6_SHIFT,
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GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
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GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
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}
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#endif
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__weak int rk3288_board_late_init(void)
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{
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return 0;
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}
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int rk_board_late_init(void)
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{
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return rk3288_board_late_init();
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}
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static int do_clock(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
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{
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static const struct {
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char *name;
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int id;
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} clks[] = {
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{ "osc", CLK_OSC },
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{ "apll", CLK_ARM },
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{ "dpll", CLK_DDR },
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{ "cpll", CLK_CODEC },
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{ "gpll", CLK_GENERAL },
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#ifdef CONFIG_ROCKCHIP_RK3036
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{ "mpll", CLK_NEW },
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#else
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{ "npll", CLK_NEW },
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#endif
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};
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int ret, i;
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struct udevice *dev;
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ret = rockchip_get_clk(&dev);
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if (ret) {
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printf("clk-uclass not found\n");
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return 0;
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}
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for (i = 0; i < ARRAY_SIZE(clks); i++) {
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struct clk clk;
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ulong rate;
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clk.id = clks[i].id;
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ret = clk_request(dev, &clk);
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if (ret < 0)
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continue;
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rate = clk_get_rate(&clk);
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printf("%s: %lu\n", clks[i].name, rate);
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clk_free(&clk);
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}
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return 0;
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}
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U_BOOT_CMD(
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clock, 2, 1, do_clock,
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"display information about clocks",
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""
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);
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