mirror of
https://github.com/AsahiLinux/u-boot
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301 lines
10 KiB
C
301 lines
10 KiB
C
/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <spd_sdram.h>
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#include <ppc4xx_enet.h>
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#include <miiphy.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern int alpr_fpga_init(void);
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int board_early_init_f (void)
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{
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/*-------------------------------------------------------------------------
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* Initialize EBC CONFIG
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*-------------------------------------------------------------------------*/
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mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
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EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
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EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
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EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
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EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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/*
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* Because of the interrupt handling rework to handle 440GX interrupts
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* with the common code, we needed to change names of the UIC registers.
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* Here the new relationship:
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*
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* U-Boot name 440GX name
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* -----------------------
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* UIC0 UICB0
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* UIC1 UIC0
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* UIC2 UIC1
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* UIC3 UIC2
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*/
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic1er, 0x00000000); /* disable all */
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mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
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mtdcr (uic1pr, 0xfffffe03); /* per manual */
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mtdcr (uic1tr, 0x01c00000); /* per manual */
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mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uic2er, 0x00000000); /* disable all */
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mtdcr (uic2cr, 0x00000000); /* all non-critical */
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mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
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mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uic3sr, 0xffffffff); /* clear all */
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mtdcr (uic3er, 0x00000000); /* disable all */
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mtdcr (uic3cr, 0x00000000); /* all non-critical */
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mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
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mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
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mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic3sr, 0xffffffff); /* clear all */
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mtdcr (uic0sr, 0xfc000000); /* clear all */
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mtdcr (uic0er, 0x00000000); /* disable all */
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mtdcr (uic0cr, 0x00000000); /* all non-critical */
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mtdcr (uic0pr, 0xfc000000); /* */
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mtdcr (uic0tr, 0x00000000); /* */
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mtdcr (uic0vr, 0x00000001); /* */
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/* Setup shutdown/SSD empty interrupt as inputs */
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
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/* Setup GPIO/IRQ multiplexing */
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mtsdr(sdr_pfc0, 0x01a33e00);
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return 0;
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}
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int last_stage_init(void)
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{
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unsigned short reg;
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/*
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* Configure LED's of both Marvell 88E1111 PHY's
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*
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* This has to be done after the 4xx ethernet driver is loaded,
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* so "last_stage_init()" is the right place.
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*/
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miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®);
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reg |= 0x0001;
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miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
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miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®);
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reg |= 0x0001;
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miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
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return 0;
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}
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static int board_rev(void)
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{
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/* Setup as input */
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
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return (in32(GPIO0_IR) >> 16) & 0x3;
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}
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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printf ("Board: ALPR");
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if (s != NULL) {
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puts (", serial# ");
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puts (s);
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}
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printf(" (Rev. %d)\n", board_rev());
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return (0);
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}
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int pci_pre_init(struct pci_controller * hose )
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{
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unsigned long strap;
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/*--------------------------------------------------------------------------+
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* The ocotea board is always configured as the host & requires the
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* PCI arbiter to be enabled.
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*--------------------------------------------------------------------------*/
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mfsdr(sdr_sdstp1, strap);
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if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
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printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
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return 0;
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}
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/* FPGA Init */
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alpr_fpga_init ();
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return 1;
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}
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#endif /* defined(CONFIG_PCI) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller * hose )
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{
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/*--------------------------------------------------------------------------+
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* Disable everything
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0SA, 0 ); /* disable */
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out32r( PCIX0_PIM1SA, 0 ); /* disable */
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out32r( PCIX0_PIM2SA, 0 ); /* disable */
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out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
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/*--------------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
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* options to not support sizes such as 128/256 MB.
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
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out32r( PCIX0_PIM0LAH, 0 );
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out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
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out32r( PCIX0_BAR0, 0 );
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/*--------------------------------------------------------------------------+
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* Program the board's subsystem id/vendor id
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*--------------------------------------------------------------------------*/
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out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
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out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
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out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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}
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
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/*************************************************************************
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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static void wait_for_pci_ready(void)
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{
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/*
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* Configure EREADY as input
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*/
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY);
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udelay(1000);
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for (;;) {
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if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY)
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return;
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}
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}
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int is_pci_host(struct pci_controller *hose)
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{
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wait_for_pci_ready();
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return 1; /* return 1 for host controller */
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}
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#endif /* defined(CONFIG_PCI) */
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/*************************************************************************
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* pci_master_init
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
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void pci_master_init(struct pci_controller *hose)
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{
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/*--------------------------------------------------------------------------+
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| PowerPC440 PCI Master configuration.
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| Map PLB/processor addresses to PCI memory space.
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| PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
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| Use byte reversed out routines to handle endianess.
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| Make this region non-prefetchable.
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+--------------------------------------------------------------------------*/
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out32r( PCIX0_POM0SA, 0 ); /* disable */
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out32r( PCIX0_POM1SA, 0 ); /* disable */
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out32r( PCIX0_POM2SA, 0 ); /* disable */
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out32r(PCIX0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
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out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */
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out32r(PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
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out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
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out32r(PCIX0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
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out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */
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out32r(PCIX0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
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out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
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}
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
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#ifdef CONFIG_POST
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/*
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* Returns 1 if keys pressed to start the power-on long-running tests
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* Called from board_init_f().
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*/
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int post_hotkeys_pressed(void)
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{
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return (ctrlc());
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}
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#endif
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