mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
295326231d
For Electro-Magnetic Compatibility. Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
19 lines
518 B
C
19 lines
518 B
C
/*
|
|
* Copyright (C) 2016 Socionext Inc.
|
|
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include "../init.h"
|
|
#include "../sc64-regs.h"
|
|
#include "pll.h"
|
|
|
|
int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd)
|
|
{
|
|
uniphier_ld20_sscpll_init(SC_DPLL0CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
|
|
uniphier_ld20_sscpll_init(SC_DPLL1CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
|
|
uniphier_ld20_sscpll_init(SC_DPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
|
|
|
|
return 0;
|
|
}
|