mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
2f1f797efa
Add device trees for 96boards EE DeveloperBox and basement SynQuacer SoC dtsi. These files are imported from EDK2 commit 83d38b0b4c0f240d4488c600bbe87cea391f3922 as-is (except for the changes #include path and some macros). And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
73 lines
1.6 KiB
Text
73 lines
1.6 KiB
Text
/** @file
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* Copyright (c) 2018, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*/
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#define __L1(cpuref, l2ref) \
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cpuref { \
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i-cache-size = <0x8000>; \
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i-cache-line-size = <64>; \
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i-cache-sets = <256>; \
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d-cache-size = <0x8000>; \
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d-cache-line-size = <64>; \
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d-cache-sets = <128>; \
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l2-cache = <l2ref>; \
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};
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#define __L2(idx) \
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L2_##idx: l2-cache##idx { \
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cache-size = <0x40000>; \
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cache-line-size = <64>; \
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cache-sets = <256>; \
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cache-unified; \
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next-level-cache = <&L3>; \
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};
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/ {
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__L2(0)
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__L2(1)
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__L2(2)
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__L2(3)
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__L2(4)
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__L2(5)
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__L2(6)
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__L2(7)
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__L2(8)
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__L2(9)
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__L2(10)
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__L2(11)
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L3: l3-cache {
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cache-level = <3>;
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cache-size = <0x400000>;
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cache-line-size = <64>;
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cache-sets = <4096>;
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cache-unified;
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};
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};
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__L1(&CPU0, &L2_0)
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__L1(&CPU1, &L2_0)
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__L1(&CPU2, &L2_1)
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__L1(&CPU3, &L2_1)
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__L1(&CPU4, &L2_2)
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__L1(&CPU5, &L2_2)
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__L1(&CPU6, &L2_3)
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__L1(&CPU7, &L2_3)
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__L1(&CPU8, &L2_4)
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__L1(&CPU9, &L2_4)
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__L1(&CPU10, &L2_5)
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__L1(&CPU11, &L2_5)
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__L1(&CPU12, &L2_6)
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__L1(&CPU13, &L2_6)
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__L1(&CPU14, &L2_7)
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__L1(&CPU15, &L2_7)
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__L1(&CPU16, &L2_8)
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__L1(&CPU17, &L2_8)
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__L1(&CPU18, &L2_9)
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__L1(&CPU19, &L2_9)
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__L1(&CPU20, &L2_10)
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__L1(&CPU21, &L2_10)
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__L1(&CPU22, &L2_11)
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__L1(&CPU23, &L2_11)
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