mirror of
https://github.com/AsahiLinux/u-boot
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245 lines
7 KiB
Text
245 lines
7 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
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*
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* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clk/at91.h>
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/{
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model = "Microchip SAM9X60 SoC";
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compatible = "microchip,sam9x60";
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aliases {
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serial0 = &dbgu;
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gpio0 = &pioA;
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gpio1 = &pioB;
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gpio2 = &pioC;
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gpio3 = &pioD;
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spi0 = &qspi;
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};
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clocks {
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slow_rc_osc: slow_rc_osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <18500>;
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};
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main_rc: main_rc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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ARM9260_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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clocks = <&pmc PMC_TYPE_CORE 19>, <&pmc PMC_TYPE_CORE 11>, <&main_xtal>;
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clock-names = "cpu", "master", "xtal";
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sdhci0: sdhci-host@80000000 {
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compatible = "microchip,sam9x60-sdhci";
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reg = <0x80000000 0x300>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
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clock-names = "hclock", "multclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
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assigned-clock-rates = <100000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci0>;
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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qspi: spi@f0014000 {
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compatible = "microchip,sam9x60-qspi";
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reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
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reg-names = "qspi_base", "qspi_mmap";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 18>; /* ID_QSPI */
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clock-names = "pclk", "qspick";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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flx0: flexcom@f801c600 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xf801c000 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xf801c000 0x800>;
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status = "disabled";
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};
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macb0: ethernet@f802c000 {
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compatible = "cdns,sam9x60-macb", "cdns,macb";
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reg = <0xf802c000 0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_macb0_rmii>;
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clock-names = "hclk", "pclk";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
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status = "disabled";
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};
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dbgu: serial@fffff200 {
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compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
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reg = <0xfffff200 0x200>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dbgu>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
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clock-names = "usart";
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};
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pinctrl {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "microchip,sam9x60-pinctrl", "simple-bus";
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ranges = <0xfffff400 0xfffff400 0x800>;
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reg = <0xfffff400 0x200 /* pioA */
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0xfffff600 0x200 /* pioB */
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0xfffff800 0x200 /* pioC */
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0xfffffa00 0x200>; /* pioD */
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/* shared pinctrl settings */
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dbgu {
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pinctrl_dbgu: dbgu-0 {
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atmel,pins =
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<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
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AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
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};
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};
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macb0 {
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pinctrl_macb0_rmii: macb0_rmii-0 {
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atmel,pins =
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<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
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AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
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AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
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AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
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AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
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AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
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AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
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AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
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AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
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AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
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};
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};
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sdhci0 {
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pinctrl_sdhci0: sdhci0 {
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atmel,pins =
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<AT91_PIOA 17 AT91_PERIPH_A
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(AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */
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AT91_PIOA 16 AT91_PERIPH_A
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(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */
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AT91_PIOA 15 AT91_PERIPH_A
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(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */
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AT91_PIOA 18 AT91_PERIPH_A
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(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */
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AT91_PIOA 19 AT91_PERIPH_A
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(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */
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AT91_PIOA 20 AT91_PERIPH_A
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(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */
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};
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};
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};
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pioA: gpio@fffff400 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffff400 0x200>;
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#gpio-cells = <2>;
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gpio-controller;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
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};
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pioB: gpio@fffff600 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffff600 0x200>;
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#gpio-cells = <2>;
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gpio-controller;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
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};
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pioC: gpio@fffff800 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffff800 0x200>;
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#gpio-cells = <2>;
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gpio-controller;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
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};
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pioD: gpio@fffffa00 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffffa00 0x200>;
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#gpio-cells = <2>;
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gpio-controller;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
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};
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pmc: pmc@fffffc00 {
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compatible = "microchip,sam9x60-pmc";
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reg = <0xfffffc00 0x200>;
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#clock-cells = <2>;
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clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
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clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
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status = "okay";
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};
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pit: timer@fffffe40 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffe40 0x10>;
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clocks = <&pmc PMC_TYPE_CORE 11>; /* ID_MCK. */
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};
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clk32: sckc@fffffe50 {
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compatible = "microchip,sam9x60-sckc";
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reg = <0xfffffe50 0x4>;
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clocks = <&slow_rc_osc>, <&slow_xtal>;
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#clock-cells = <1>;
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};
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};
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};
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onewire_tm: onewire {
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compatible = "w1-gpio";
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status = "disabled";
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};
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};
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