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https://github.com/AsahiLinux/u-boot
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e3b326fee5
This patch adds mmc related nodes for mt7628an.dtsi Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
407 lines
7.1 KiB
Text
407 lines
7.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/clock/mt7628-clk.h>
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#include <dt-bindings/reset/mt7628-reset.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ralink,mt7628a-soc";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mti,mips24KEc";
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device_type = "cpu";
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reg = <0>;
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};
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};
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cpuintc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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clk48m: clk48m@0 {
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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#clock-cells = <0>;
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};
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palmbus@10000000 {
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compatible = "palmbus", "simple-bus";
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reg = <0x10000000 0x200000>;
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ranges = <0x0 0x10000000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc: system-controller@0 {
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compatible = "ralink,mt7620a-sysc", "syscon";
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reg = <0x0 0x100>;
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};
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syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&sysc>;
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offset = <0x34>;
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mask = <0x1>;
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};
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clkctrl: clkctrl@0x2c {
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reg = <0x2c 0x8>, <0x10 0x4>;
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reg-names = "syscfg0", "clkcfg";
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compatible = "mediatek,mt7628-clk";
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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rstctrl: rstctrl@0x34 {
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reg = <0x34 0x4>;
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compatible = "mediatek,mtmips-reset";
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#reset-cells = <1>;
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};
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pinctrl: pinctrl@60 {
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compatible = "mediatek,mt7628-pinctrl";
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reg = <0x3c 0x2c>, <0x1300 0x100>;
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reg-names = "gpiomode", "padconf";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pin_state {
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};
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spi_single_pins: spi_single_pins {
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groups = "spi";
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function = "spi";
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};
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spi_dual_pins: spi_dual_pins {
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spi_master_pins {
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groups = "spi";
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function = "spi";
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};
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spi_cs1_pin {
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groups = "spi cs1";
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function = "spi cs1";
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};
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};
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uart0_pins: uart0_pins {
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groups = "uart0";
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function = "uart0";
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};
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uart1_pins: uart1_pins {
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groups = "uart1";
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function = "uart1";
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};
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uart2_pins: uart2_pins {
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groups = "uart2";
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function = "uart2";
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};
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i2c_pins: i2c_pins {
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groups = "i2c";
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function = "i2c";
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};
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ephy_iot_mode: ephy_iot_mode {
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ephy4_1_dis {
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groups = "ephy4_1_pad";
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function = "digital";
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};
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ephy0_en {
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groups = "ephy0";
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function = "enable";
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};
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};
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ephy_router_mode: ephy_router_mode {
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ephy4_1_en {
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groups = "ephy4_1_pad";
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function = "analog";
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};
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ephy0_en {
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groups = "ephy0";
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function = "enable";
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};
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};
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sd_iot_mode: sd_iot_mode {
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ephy4_1_dis {
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groups = "ephy4_1_pad";
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function = "digital";
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};
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sdxc_en {
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groups = "sdmode";
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function = "sdxc";
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};
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sdxc_iot_mode {
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groups = "sd router";
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function = "iot";
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};
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sd_clk_pad {
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pins = "sd_clk";
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drive-strength-4g = <8>;
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};
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};
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sd_router_mode: sd_router_mode {
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sdxc_router_mode {
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groups = "sd router";
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function = "router";
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};
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sdxc_map_pins {
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groups = "gpio0", "i2s", "sdmode", \
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"i2c", "uart1";
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function = "gpio";
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};
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sd_clk_pad {
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pins = "gpio0";
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drive-strength-28 = <8>;
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};
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};
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emmc_iot_8bit_mode: emmc_iot_8bit_mode {
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ephy4_1_dis {
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groups = "ephy4_1_pad";
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function = "digital";
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};
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emmc_en {
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groups = "sdmode";
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function = "sdxc";
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};
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emmc_iot_mode {
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groups = "sd router";
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function = "iot";
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};
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emmc_d4_d5 {
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groups = "uart2";
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function = "sdxc d5 d4";
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};
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emmc_d6 {
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groups = "pwm1";
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function = "sdxc d6";
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};
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emmc_d7 {
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groups = "pwm0";
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function = "sdxc d7";
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};
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sd_clk_pad {
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pins = "sd_clk";
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drive-strength-4g = <8>;
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};
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};
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};
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watchdog: watchdog@100 {
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compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
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reg = <0x100 0x30>;
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resets = <&rstctrl MT7628_TIMER_RST>;
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reset-names = "wdt";
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interrupt-parent = <&intc>;
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interrupts = <24>;
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};
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intc: interrupt-controller@200 {
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compatible = "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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resets = <&rstctrl MT7628_INT_RST>;
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reset-names = "intc";
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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ralink,intc-registers = <0x9c 0xa0
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0x6c 0xa4
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0x80 0x78>;
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};
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memory-controller@300 {
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compatible = "ralink,mt7620a-memc";
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reg = <0x300 0x100>;
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};
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gpio@600 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
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reg = <0x600 0x100>;
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resets = <&rstctrl MT7628_PIO_RST>;
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reset-names = "pio";
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interrupt-parent = <&intc>;
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interrupts = <6>;
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gpio0: bank@0 {
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reg = <0>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: bank@1 {
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reg = <1>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: bank@2 {
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reg = <2>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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spi0: spi@b00 {
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compatible = "ralink,mt7621-spi";
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reg = <0xb00 0x40>;
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resets = <&rstctrl MT7628_SPI_RST>;
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reset-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkctrl CLK_SPI>;
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};
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uart0: uartlite@c00 {
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compatible = "mediatek,hsuart", "ns16550a";
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reg = <0xc00 0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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clocks = <&clkctrl CLK_UART0>;
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resets = <&rstctrl MT7628_UART0_RST>;
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reset-names = "uart0";
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interrupt-parent = <&intc>;
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interrupts = <20>;
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reg-shift = <2>;
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};
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uart1: uart1@d00 {
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compatible = "mediatek,hsuart", "ns16550a";
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reg = <0xd00 0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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clocks = <&clkctrl CLK_UART1>;
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resets = <&rstctrl MT7628_UART1_RST>;
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reset-names = "uart1";
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interrupt-parent = <&intc>;
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interrupts = <21>;
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reg-shift = <2>;
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};
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uart2: uart2@e00 {
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compatible = "mediatek,hsuart", "ns16550a";
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reg = <0xe00 0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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clocks = <&clkctrl CLK_UART2>;
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resets = <&rstctrl MT7628_UART2_RST>;
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reset-names = "uart2";
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interrupt-parent = <&intc>;
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interrupts = <22>;
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reg-shift = <2>;
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};
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};
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eth: eth@10110000 {
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compatible = "mediatek,mt7628-eth";
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reg = <0x10100000 0x10000
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0x10110000 0x8000>;
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resets = <&rstctrl MT7628_EPHY_RST>;
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reset-names = "ephy";
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syscon = <&sysc>;
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};
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usb_phy: usb-phy@10120000 {
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compatible = "mediatek,mt7628-usbphy";
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reg = <0x10120000 0x1000>;
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#phy-cells = <0>;
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ralink,sysctl = <&sysc>;
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resets = <&rstctrl MT7628_UPHY_RST>;
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reset-names = "phy";
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clocks = <&clkctrl CLK_UPHY>;
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clock-names = "cg";
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};
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ehci@101c0000 {
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compatible = "generic-ehci";
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reg = <0x101c0000 0x1000>;
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phys = <&usb_phy>;
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phy-names = "usb";
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interrupt-parent = <&intc>;
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interrupts = <18>;
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};
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mmc: mmc@10130000 {
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compatible = "mediatek,mt7620-mmc";
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reg = <0x10130000 0x4000>;
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builtin-cd = <1>;
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r_smpl = <1>;
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clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
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clock-names = "source", "hclk";
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resets = <&rstctrl MT7628_SDXC_RST>;
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status = "disabled";
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};
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};
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