mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
29caf9305b
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
452 lines
11 KiB
C
452 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek High-speed UART driver
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*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <serial.h>
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#include <watchdog.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <linux/err.h>
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struct mtk_serial_regs {
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u32 rbr;
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u32 ier;
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u32 fcr;
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u32 lcr;
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u32 mcr;
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u32 lsr;
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u32 msr;
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u32 spr;
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u32 mdr1;
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u32 highspeed;
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u32 sample_count;
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u32 sample_point;
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u32 fracdiv_l;
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u32 fracdiv_m;
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u32 escape_en;
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u32 guard;
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u32 rx_sel;
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};
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#define thr rbr
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#define iir fcr
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#define dll rbr
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#define dlm ier
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#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LSR_DR 0x01 /* Data ready */
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#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
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#define UART_LSR_TEMT 0x40 /* Xmitter empty */
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#define UART_MCR_DTR 0x01 /* DTR */
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#define UART_MCR_RTS 0x02 /* RTS */
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#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
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#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
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#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
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#define UART_MCRVAL (UART_MCR_DTR | \
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UART_MCR_RTS)
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/* Clear & enable FIFOs */
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#define UART_FCRVAL (UART_FCR_FIFO_EN | \
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UART_FCR_RXSR | \
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UART_FCR_TXSR)
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/* the data is correct if the real baud is within 3%. */
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#define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100)
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#define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100)
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struct mtk_serial_priv {
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struct mtk_serial_regs __iomem *regs;
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u32 clock;
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bool force_highspeed;
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};
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static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud)
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{
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u32 quot, realbaud, samplecount = 1;
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/* Special case for low baud clock */
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if (baud <= 115200 && priv->clock <= 12000000) {
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writel(3, &priv->regs->highspeed);
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quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud);
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if (quot == 0)
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quot = 1;
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samplecount = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
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realbaud = priv->clock / samplecount / quot;
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if (realbaud > BAUD_ALLOW_MAX(baud) ||
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realbaud < BAUD_ALLOW_MIX(baud)) {
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pr_info("baud %d can't be handled\n", baud);
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}
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goto set_baud;
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}
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if (priv->force_highspeed)
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goto use_hs3;
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if (baud <= 115200) {
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writel(0, &priv->regs->highspeed);
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quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud);
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} else if (baud <= 576000) {
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writel(2, &priv->regs->highspeed);
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/* Set to next lower baudrate supported */
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if ((baud == 500000) || (baud == 576000))
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baud = 460800;
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quot = DIV_ROUND_UP(priv->clock, 4 * baud);
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} else {
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use_hs3:
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writel(3, &priv->regs->highspeed);
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quot = DIV_ROUND_UP(priv->clock, 256 * baud);
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samplecount = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
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}
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set_baud:
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/* set divisor */
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writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr);
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writel(quot & 0xff, &priv->regs->dll);
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writel((quot >> 8) & 0xff, &priv->regs->dlm);
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writel(UART_LCR_WLS_8, &priv->regs->lcr);
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/* set highspeed mode sample count & point */
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writel(samplecount - 1, &priv->regs->sample_count);
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writel((samplecount - 2) >> 1, &priv->regs->sample_point);
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}
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static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
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{
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if (!(readl(&priv->regs->lsr) & UART_LSR_THRE))
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return -EAGAIN;
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writel(ch, &priv->regs->thr);
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if (ch == '\n')
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schedule();
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return 0;
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}
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static int _mtk_serial_getc(struct mtk_serial_priv *priv)
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{
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if (!(readl(&priv->regs->lsr) & UART_LSR_DR))
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return -EAGAIN;
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return readl(&priv->regs->rbr);
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}
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static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input)
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{
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if (input)
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return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0;
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else
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return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
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}
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#if defined(CONFIG_DM_SERIAL) && \
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(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_DM))
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static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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_mtk_serial_setbrg(priv, baudrate);
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return 0;
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}
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static int mtk_serial_putc(struct udevice *dev, const char ch)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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return _mtk_serial_putc(priv, ch);
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}
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static int mtk_serial_getc(struct udevice *dev)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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return _mtk_serial_getc(priv);
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}
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static int mtk_serial_pending(struct udevice *dev, bool input)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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return _mtk_serial_pending(priv, input);
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}
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static int mtk_serial_probe(struct udevice *dev)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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/* Disable interrupt */
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writel(0, &priv->regs->ier);
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writel(UART_MCRVAL, &priv->regs->mcr);
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writel(UART_FCRVAL, &priv->regs->fcr);
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return 0;
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}
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static int mtk_serial_of_to_plat(struct udevice *dev)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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struct clk clk;
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int err;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = map_physmem(addr, 0, MAP_NOCACHE);
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err = clk_get_by_index(dev, 0, &clk);
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if (!err) {
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err = clk_get_rate(&clk);
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if (!IS_ERR_VALUE(err))
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priv->clock = err;
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} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
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debug("mtk_serial: failed to get clock\n");
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return err;
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}
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if (!priv->clock)
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priv->clock = dev_read_u32_default(dev, "clock-frequency", 0);
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if (!priv->clock) {
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debug("mtk_serial: clock not defined\n");
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return -EINVAL;
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}
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priv->force_highspeed = dev_read_bool(dev, "mediatek,force-highspeed");
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return 0;
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}
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static const struct dm_serial_ops mtk_serial_ops = {
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.putc = mtk_serial_putc,
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.pending = mtk_serial_pending,
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.getc = mtk_serial_getc,
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.setbrg = mtk_serial_setbrg,
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};
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static const struct udevice_id mtk_serial_ids[] = {
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{ .compatible = "mediatek,hsuart" },
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{ .compatible = "mediatek,mt6577-uart" },
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{ }
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};
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U_BOOT_DRIVER(serial_mtk) = {
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.name = "serial_mtk",
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.id = UCLASS_SERIAL,
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.of_match = mtk_serial_ids,
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.of_to_plat = mtk_serial_of_to_plat,
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.priv_auto = sizeof(struct mtk_serial_priv),
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.probe = mtk_serial_probe,
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.ops = &mtk_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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#else
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DECLARE_GLOBAL_DATA_PTR;
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#define DECLARE_HSUART_PRIV(port) \
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static struct mtk_serial_priv mtk_hsuart##port = { \
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.regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \
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.clock = CONFIG_SYS_NS16550_CLK \
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};
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#define DECLARE_HSUART_FUNCTIONS(port) \
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static int mtk_serial##port##_init(void) \
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{ \
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writel(0, &mtk_hsuart##port.regs->ier); \
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writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \
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writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \
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_mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
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return 0 ; \
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} \
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static void mtk_serial##port##_setbrg(void) \
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{ \
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_mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
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} \
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static int mtk_serial##port##_getc(void) \
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{ \
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int err; \
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do { \
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err = _mtk_serial_getc(&mtk_hsuart##port); \
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if (err == -EAGAIN) \
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schedule(); \
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} while (err == -EAGAIN); \
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return err >= 0 ? err : 0; \
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} \
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static int mtk_serial##port##_tstc(void) \
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{ \
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return _mtk_serial_pending(&mtk_hsuart##port, true); \
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} \
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static void mtk_serial##port##_putc(const char c) \
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{ \
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int err; \
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if (c == '\n') \
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mtk_serial##port##_putc('\r'); \
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do { \
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err = _mtk_serial_putc(&mtk_hsuart##port, c); \
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} while (err == -EAGAIN); \
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} \
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static void mtk_serial##port##_puts(const char *s) \
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{ \
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while (*s) { \
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mtk_serial##port##_putc(*s++); \
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} \
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}
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/* Serial device descriptor */
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#define INIT_HSUART_STRUCTURE(port, __name) { \
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.name = __name, \
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.start = mtk_serial##port##_init, \
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.stop = NULL, \
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.setbrg = mtk_serial##port##_setbrg, \
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.getc = mtk_serial##port##_getc, \
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.tstc = mtk_serial##port##_tstc, \
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.putc = mtk_serial##port##_putc, \
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.puts = mtk_serial##port##_puts, \
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}
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#define DECLARE_HSUART(port, __name) \
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DECLARE_HSUART_PRIV(port); \
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DECLARE_HSUART_FUNCTIONS(port); \
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struct serial_device mtk_hsuart##port##_device = \
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INIT_HSUART_STRUCTURE(port, __name);
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#if !defined(CONFIG_CONS_INDEX)
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#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6)
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#error "Invalid console index value."
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#endif
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#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
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#error "Console port 1 defined but not configured."
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#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
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#error "Console port 2 defined but not configured."
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#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
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#error "Console port 3 defined but not configured."
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#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
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#error "Console port 4 defined but not configured."
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#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
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#error "Console port 5 defined but not configured."
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#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
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#error "Console port 6 defined but not configured."
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#endif
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#if defined(CONFIG_SYS_NS16550_COM1)
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DECLARE_HSUART(1, "mtk-hsuart0");
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#endif
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#if defined(CONFIG_SYS_NS16550_COM2)
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DECLARE_HSUART(2, "mtk-hsuart1");
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#endif
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#if defined(CONFIG_SYS_NS16550_COM3)
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DECLARE_HSUART(3, "mtk-hsuart2");
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#endif
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#if defined(CONFIG_SYS_NS16550_COM4)
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DECLARE_HSUART(4, "mtk-hsuart3");
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#endif
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#if defined(CONFIG_SYS_NS16550_COM5)
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DECLARE_HSUART(5, "mtk-hsuart4");
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#endif
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#if defined(CONFIG_SYS_NS16550_COM6)
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DECLARE_HSUART(6, "mtk-hsuart5");
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#endif
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__weak struct serial_device *default_serial_console(void)
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{
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#if CONFIG_CONS_INDEX == 1
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return &mtk_hsuart1_device;
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#elif CONFIG_CONS_INDEX == 2
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return &mtk_hsuart2_device;
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#elif CONFIG_CONS_INDEX == 3
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return &mtk_hsuart3_device;
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#elif CONFIG_CONS_INDEX == 4
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return &mtk_hsuart4_device;
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#elif CONFIG_CONS_INDEX == 5
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return &mtk_hsuart5_device;
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#elif CONFIG_CONS_INDEX == 6
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return &mtk_hsuart6_device;
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#else
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#error "Bad CONFIG_CONS_INDEX."
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#endif
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}
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void mtk_serial_initialize(void)
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{
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#if defined(CONFIG_SYS_NS16550_COM1)
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serial_register(&mtk_hsuart1_device);
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#endif
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#if defined(CONFIG_SYS_NS16550_COM2)
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serial_register(&mtk_hsuart2_device);
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#endif
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#if defined(CONFIG_SYS_NS16550_COM3)
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serial_register(&mtk_hsuart3_device);
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#endif
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#if defined(CONFIG_SYS_NS16550_COM4)
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serial_register(&mtk_hsuart4_device);
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#endif
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#if defined(CONFIG_SYS_NS16550_COM5)
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serial_register(&mtk_hsuart5_device);
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#endif
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#if defined(CONFIG_SYS_NS16550_COM6)
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serial_register(&mtk_hsuart6_device);
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#endif
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}
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#endif
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#ifdef CONFIG_DEBUG_UART_MTK
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#include <debug_uart.h>
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static inline void _debug_uart_init(void)
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{
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struct mtk_serial_priv priv;
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priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
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priv.clock = CONFIG_DEBUG_UART_CLOCK;
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writel(0, &priv.regs->ier);
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writel(UART_MCRVAL, &priv.regs->mcr);
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writel(UART_FCRVAL, &priv.regs->fcr);
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_mtk_serial_setbrg(&priv, CONFIG_BAUDRATE);
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}
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static inline void _debug_uart_putc(int ch)
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{
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struct mtk_serial_regs __iomem *regs =
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(void *) CONFIG_VAL(DEBUG_UART_BASE);
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while (!(readl(®s->lsr) & UART_LSR_THRE))
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;
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writel(ch, ®s->thr);
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}
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DEBUG_UART_FUNCS
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#endif
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