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https://github.com/AsahiLinux/u-boot
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279 lines
7.1 KiB
C
279 lines
7.1 KiB
C
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
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*/
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#include <common.h>
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#include <command.h>
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#include <mpc8260.h>
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#include <mpc8260_irq.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/****************************************************************************/
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struct irq_action {
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interrupt_handler_t *handler;
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void *arg;
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ulong count;
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};
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static struct irq_action irq_handlers[NR_IRQS];
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static ulong ppc_cached_irq_mask[NR_MASK_WORDS];
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/****************************************************************************/
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/* this section was ripped out of arch/ppc/kernel/ppc8260_pic.c in the */
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/* Linux/PPC 2.4.x source. There was no copyright notice in that file. */
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/* The 8260 internal interrupt controller. It is usually
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* the only interrupt controller.
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* There are two 32-bit registers (high/low) for up to 64
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* possible interrupts.
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*
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* Now, the fun starts.....Interrupt Numbers DO NOT MAP
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* in a simple arithmetic fashion to mask or pending registers.
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* That is, interrupt 4 does not map to bit position 4.
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* We create two tables, indexed by vector number, to indicate
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* which register to use and which bit in the register to use.
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*/
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static u_char irq_to_siureg[] = {
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0
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};
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static u_char irq_to_siubit[] = {
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31, 16, 17, 18, 19, 20, 21, 22,
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23, 24, 25, 26, 27, 28, 29, 30,
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29, 30, 16, 17, 18, 19, 20, 21,
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22, 23, 24, 25, 26, 27, 28, 31,
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0, 1, 2, 3, 4, 5, 6, 7,
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8, 9, 10, 11, 12, 13, 14, 15,
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15, 14, 13, 12, 11, 10, 9, 8,
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7, 6, 5, 4, 3, 2, 1, 0
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};
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static void m8260_mask_irq (unsigned int irq_nr)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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int bit, word;
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volatile uint *simr;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(immr->im_intctl.ic_simrh);
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ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
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simr[word] = ppc_cached_irq_mask[word];
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}
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static void m8260_unmask_irq (unsigned int irq_nr)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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int bit, word;
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volatile uint *simr;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(immr->im_intctl.ic_simrh);
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ppc_cached_irq_mask[word] |= (1 << (31 - bit));
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simr[word] = ppc_cached_irq_mask[word];
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}
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static void m8260_mask_and_ack (unsigned int irq_nr)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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int bit, word;
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volatile uint *simr, *sipnr;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(immr->im_intctl.ic_simrh);
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sipnr = &(immr->im_intctl.ic_sipnrh);
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ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
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simr[word] = ppc_cached_irq_mask[word];
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sipnr[word] = 1 << (31 - bit);
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}
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static int m8260_get_irq (struct pt_regs *regs)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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int irq;
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unsigned long bits;
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/* For MPC8260, read the SIVEC register and shift the bits down
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* to get the irq number. */
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bits = immr->im_intctl.ic_sivec;
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irq = bits >> 26;
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return irq;
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}
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/* end of code ripped out of arch/ppc/kernel/ppc8260_pic.c */
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/****************************************************************************/
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int interrupt_init_cpu (unsigned *decrementer_count)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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*decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
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/* Initialize the default interrupt mapping priorities */
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immr->im_intctl.ic_sicr = 0;
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immr->im_intctl.ic_siprr = 0x05309770;
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immr->im_intctl.ic_scprrh = 0x05309770;
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immr->im_intctl.ic_scprrl = 0x05309770;
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/* disable all interrupts and clear all pending bits */
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immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0;
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immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0;
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immr->im_intctl.ic_sipnrh = 0xffffffff;
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immr->im_intctl.ic_sipnrl = 0xffffffff;
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#ifdef CONFIG_HYMOD
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/*
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* ensure all external interrupt sources default to trigger on
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* high-to-low transition (i.e. edge triggered active low)
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*/
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immr->im_intctl.ic_siexr = -1;
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#endif
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return (0);
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}
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/****************************************************************************/
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/*
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* Handle external interrupts
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*/
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void external_interrupt (struct pt_regs *regs)
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{
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int irq, unmask = 1;
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irq = m8260_get_irq (regs);
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m8260_mask_and_ack (irq);
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enable_interrupts ();
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if (irq_handlers[irq].handler != NULL)
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(*irq_handlers[irq].handler) (irq_handlers[irq].arg);
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else {
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printf ("\nBogus External Interrupt IRQ %d\n", irq);
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/*
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* turn off the bogus interrupt, otherwise it
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* might repeat forever
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*/
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unmask = 0;
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}
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if (unmask)
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m8260_unmask_irq (irq);
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}
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/****************************************************************************/
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/*
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* Install and free an interrupt handler.
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*/
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void
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irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
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{
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if (irq < 0 || irq >= NR_IRQS) {
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printf ("irq_install_handler: bad irq number %d\n", irq);
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return;
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}
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if (irq_handlers[irq].handler != NULL)
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printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
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(ulong) handler, (ulong) irq_handlers[irq].handler);
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irq_handlers[irq].handler = handler;
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irq_handlers[irq].arg = arg;
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m8260_unmask_irq (irq);
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}
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void irq_free_handler (int irq)
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{
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if (irq < 0 || irq >= NR_IRQS) {
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printf ("irq_free_handler: bad irq number %d\n", irq);
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return;
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}
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m8260_mask_irq (irq);
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irq_handlers[irq].handler = NULL;
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irq_handlers[irq].arg = NULL;
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}
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/****************************************************************************/
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void timer_interrupt_cpu (struct pt_regs *regs)
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{
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/* nothing to do here */
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return;
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}
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/****************************************************************************/
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#if defined(CONFIG_CMD_IRQ)
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/* ripped this out of ppc4xx/interrupts.c */
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/*******************************************************************************
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*
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* irqinfo - print information about PCI devices
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*
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*/
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void
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do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
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{
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int irq, re_enable;
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re_enable = disable_interrupts ();
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puts ("\nInterrupt-Information:\n"
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"Nr Routine Arg Count\n");
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for (irq = 0; irq < 32; irq++)
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if (irq_handlers[irq].handler != NULL)
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printf ("%02d %08lx %08lx %ld\n", irq,
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(ulong) irq_handlers[irq].handler,
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(ulong) irq_handlers[irq].arg,
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irq_handlers[irq].count);
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if (re_enable)
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enable_interrupts ();
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}
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#endif
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