mirror of
https://github.com/AsahiLinux/u-boot
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130 lines
3.1 KiB
Text
130 lines
3.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC.
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*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Eugen Hristev <eugen.hristev@microchip.com>
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/clk/at91.h>
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/ {
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model = "Microchip SAMA7G5 family SoC";
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compatible = "microchip,sama7g5";
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clocks {
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slow_rc_osc: slow_rc_osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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};
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main_rc: main_rc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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A7_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>;
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clock-names = "cpu", "master", "xtal";
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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pioA: pinctrl@e0014000 {
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compatible = "atmel,sama5d2-gpio";
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reg = <0xe0014000 0x800>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
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status = "okay";
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pinctrl: pinctrl_default {
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compatible = "microchip,sama7g5-pinctrl";
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};
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};
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pmc: pmc@e0018000 {
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compatible = "microchip,sama7g5-pmc";
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reg = <0xe0018000 0x200>;
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#clock-cells = <2>;
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clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
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clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
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status = "okay";
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};
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clk32: sckc@e001d050 {
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compatible = "microchip,sam9x60-sckc";
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reg = <0xe001d050 0x4>;
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clocks = <&slow_rc_osc>, <&slow_xtal>;
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#clock-cells = <1>;
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};
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sdmmc1: sdio-host@e1208000 {
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compatible = "microchip,sama7g5-sdhci";
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reg = <0xe1208000 0x300>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
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clock-names = "hclock", "multclk";
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status = "disabled";
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};
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pit64b0: timer@e1800000 {
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compatible = "microchip,sama7g5-pit64b";
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reg = <0xe1800000 0x4000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
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clock-names = "pclk", "gclk";
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status = "okay";
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};
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uart0: serial@e1824200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xe1824200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
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clock-names = "usart";
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status = "disabled";
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};
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gmac0: ethernet@e2800000 {
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compatible = "cdns,sama7g5-gem";
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reg = <0xe2800000 0x4000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>;
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clock-names = "hclk", "pclk", "tx_clk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */
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assigned-clock-rates = <125000000>;
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status = "disabled";
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};
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};
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};
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};
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