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https://github.com/AsahiLinux/u-boot
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3e3332130f
This patch adds more nand headers in two new types: 1. HSM header, used for spi-nand thru SNFI interface 2. SPIM header, used for spi-nand thru spi-mem interface The original nand header is renamed to AP header. Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
165 lines
5.2 KiB
C
165 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* MediaTek BootROM NAND header definitions
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*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _MTK_NAND_HEADERS_H
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#define _MTK_NAND_HEADERS_H
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#include <stdint.h>
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#include <stdbool.h>
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struct nand_header_info {
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uint32_t page_size;
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uint32_t spare_size;
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uint32_t gfh_offset;
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bool snfi;
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};
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/* AP BROM Header for NAND */
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union nand_boot_header {
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struct {
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char name[12];
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char version[4];
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char id[8];
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uint16_t ioif; /* I/O interface */
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uint16_t pagesize; /* NAND page size */
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uint16_t addrcycles; /* Address cycles */
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uint16_t oobsize; /* NAND page spare size */
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uint16_t pages_of_block; /* Pages of one block */
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uint16_t numblocks; /* Total blocks of NAND chip */
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uint16_t writesize_shift;
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uint16_t erasesize_shift;
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uint8_t dummy[60];
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uint8_t ecc_parity[28]; /* ECC parity of this header */
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};
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uint8_t data[0x80];
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};
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/* HSM BROM Header for NAND */
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union hsm_nand_boot_header {
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struct {
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char id[8];
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uint32_t version; /* Header version */
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uint32_t config; /* Header config */
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uint32_t sector_size; /* ECC step size */
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uint32_t fdm_size; /* User OOB size of a step */
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uint32_t fdm_ecc_size; /* ECC parity size of a step */
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uint32_t lbs;
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uint32_t page_size; /* NAND page size */
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uint32_t spare_size; /* NAND page spare size */
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uint32_t page_per_block; /* Pages of one block */
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uint32_t blocks; /* Total blocks of NAND chip */
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uint32_t plane_sel_position; /* Plane bit position */
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uint32_t pll; /* Value of pll reg */
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uint32_t acccon; /* Value of access timing reg */
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uint32_t strobe_sel; /* Value of DQS selection reg*/
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uint32_t acccon1; /* Value of access timing reg */
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uint32_t dqs_mux; /* Value of DQS mux reg */
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uint32_t dqs_ctrl; /* Value of DQS control reg */
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uint32_t delay_ctrl; /* Value of delay ctrl reg */
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uint32_t latch_lat; /* Value of latch latency reg */
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uint32_t sample_delay; /* Value of sample delay reg */
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uint32_t driving; /* Value of driving reg */
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uint32_t bl_start; /* Bootloader start addr */
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uint32_t bl_end; /* Bootloader end addr */
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uint8_t ecc_parity[42]; /* ECC parity of this header */
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};
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uint8_t data[0x8E];
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};
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/* HSM2.0 BROM Header for NAND */
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union hsm20_nand_boot_header {
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struct {
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char id[8];
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uint32_t version; /* Header version */
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uint32_t config; /* Header config */
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uint32_t sector_size; /* ECC step size */
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uint32_t fdm_size; /* User OOB size of a step */
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uint32_t fdm_ecc_size; /* ECC parity size of a step */
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uint32_t lbs;
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uint32_t page_size; /* NAND page size */
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uint32_t spare_size; /* NAND page spare size */
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uint32_t page_per_block; /* Pages of one block */
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uint32_t blocks; /* Total blocks of NAND chip */
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uint32_t plane_sel_position; /* Plane bit position */
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uint32_t pll; /* Value of pll reg */
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uint32_t acccon; /* Value of access timing reg */
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uint32_t strobe_sel; /* Value of DQS selection reg*/
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uint32_t acccon1; /* Value of access timing reg */
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uint32_t dqs_mux; /* Value of DQS mux reg */
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uint32_t dqs_ctrl; /* Value of DQS control reg */
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uint32_t delay_ctrl; /* Value of delay ctrl reg */
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uint32_t latch_lat; /* Value of latch latency reg */
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uint32_t sample_delay; /* Value of sample delay reg */
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uint32_t driving; /* Value of driving reg */
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uint32_t reserved;
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uint32_t bl0_start; /* Bootloader start addr */
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uint32_t bl0_end; /* Bootloader end addr */
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uint32_t bl0_type; /* Bootloader type */
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uint8_t bl_reserve[84];
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uint8_t ecc_parity[42]; /* ECC parity of this header */
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};
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uint8_t data[0xEA];
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};
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/* SPIM BROM Header for SPI-NAND */
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union spim_nand_boot_header {
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struct {
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char id[8];
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uint32_t version; /* Header version */
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uint32_t config; /* Header config */
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uint32_t page_size; /* NAND page size */
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uint32_t spare_size; /* NAND page spare size */
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uint16_t page_per_block; /* Pages of one block */
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uint16_t plane_sel_position; /* Plane bit position */
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uint16_t reserve_reg;
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uint16_t reserve_val;
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uint16_t ecc_error; /* ECC error reg addr */
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uint16_t ecc_mask; /* ECC error bit mask */
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uint32_t bl_start; /* Bootloader start addr */
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uint32_t bl_end; /* Bootloader end addr */
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uint8_t ecc_parity[32]; /* ECC parity of this header */
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uint32_t integrity_crc; /* CRC of this header */
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};
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uint8_t data[0x50];
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};
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enum nand_boot_header_type {
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NAND_BOOT_AP_HEADER,
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NAND_BOOT_HSM_HEADER,
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NAND_BOOT_HSM20_HEADER,
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NAND_BOOT_SPIM_HEADER
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};
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#define NAND_BOOT_NAME "BOOTLOADER!"
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#define NAND_BOOT_VERSION "V006"
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#define NAND_BOOT_ID "NFIINFO"
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#define HSM_NAND_BOOT_NAME "NANDCFG!"
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#define SPIM_NAND_BOOT_NAME "SPINAND!"
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/* Find nand header data by name */
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const struct nand_header_type *mtk_nand_header_find(const char *name);
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/* Device header size using this nand header */
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uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand);
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/* Get nand info from nand header (page size, spare size, ...) */
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int mtk_nand_header_info(const void *ptr, struct nand_header_info *info);
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/* Whether given header data is valid */
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bool is_mtk_nand_header(const void *ptr);
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/* Generate Device header using give nand header */
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uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand,
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void *ptr);
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#endif /* _MTK_NAND_HEADERS_H */
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