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fe1eb9945b
In all reference designs the FCLK1 runs at 150MHz, but the bootloader doesn't set it up like that. Set the divider to 8 to generate the correct clock. Fixes (a.o.) the DMA speed being too slow. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
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zynq-topic-miami | ||
zynq-topic-miamilite | ||
zynq-topic-miamiplus | ||
board.c | ||
MAINTAINERS | ||
Makefile |