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https://github.com/AsahiLinux/u-boot
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98fe251a24
The ethernet PHY must be reset on AV96, however DWMAC currently does not support the MDIO-bus PHY GPIO reset bindings and the ethernet MAC PHY reset property is going away on next DT sync. Add PHY specific reset bindings to trigger the PHY reset and fix sporadic ethernet malfunctions, until the next DT sync. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
101 lines
1.3 KiB
Text
101 lines
1.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2020 Marek Vasut <marex@denx.de>
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*/
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#include "stm32mp15xx-dhcor-u-boot.dtsi"
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/ {
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aliases {
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mmc0 = &sdmmc1;
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mmc1 = &sdmmc2;
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usb0 = &usbotg_hs;
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};
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config {
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u-boot,boot-led = "led1";
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u-boot,error-led = "led4";
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dh,board-coding-gpios = <&gpiog 13 0>, <&gpiod 9 0>;
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};
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};
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ðernet0 {
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mdio0 {
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ethernet-phy@7 {
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reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
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reset-assert-us = <11000>;
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reset-deassert-us = <1000>;
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};
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};
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};
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&sdmmc1 {
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u-boot,dm-spl;
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st,use-ckin;
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st,cmd-gpios = <&gpiod 2 0>;
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st,ck-gpios = <&gpioc 12 0>;
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st,ckin-gpios = <&gpioe 4 0>;
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};
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&sdmmc1_b4_pins_a {
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u-boot,dm-spl;
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pins1 {
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u-boot,dm-spl;
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};
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pins2 {
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u-boot,dm-spl;
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};
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};
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&sdmmc1_dir_pins_b {
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u-boot,dm-spl;
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pins1 {
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u-boot,dm-spl;
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};
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pins2 {
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u-boot,dm-spl;
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};
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};
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&sdmmc2 {
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u-boot,dm-spl;
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};
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&sdmmc2_b4_pins_a {
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u-boot,dm-spl;
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pins1 {
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u-boot,dm-spl;
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};
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pins2 {
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u-boot,dm-spl;
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};
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};
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&sdmmc2_d47_pins_c {
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u-boot,dm-spl;
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pins {
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u-boot,dm-spl;
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};
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};
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&uart4 {
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u-boot,dm-pre-reloc;
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};
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&uart4_pins_b {
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u-boot,dm-pre-reloc;
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pins1 {
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u-boot,dm-pre-reloc;
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};
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pins2 {
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u-boot,dm-pre-reloc;
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/delete-property/ bias-disable;
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bias-pull-up;
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};
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};
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&usbotg_hs {
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u-boot,force-b-session-valid;
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hnp-srp-disable;
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};
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