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https://github.com/AsahiLinux/u-boot
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de72930433
These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
28 lines
789 B
C
28 lines
789 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _CTRL_PEX_H
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#define _CTRL_PEX_H
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#include <pci.h>
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#include "high_speed_env_spec.h"
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/* Direct access to PEX0 Root Port's PCIe Capability structure */
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#define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60)
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/* SOC_CONTROL_REG1 fields */
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#define PCIE0_ENABLE_OFFS 0
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#define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS)
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#define PCIE1_ENABLE_OFFS 1
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#define PCIE1_ENABLE_MASK (0x1 << PCIE1_ENABLE_OFFS)
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#define PCIE2_ENABLE_OFFS 2
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#define PCIE2_ENABLE_MASK (0x1 << PCIE2_ENABLE_OFFS)
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#define PCIE3_ENABLE_OFFS 3
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#define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS)
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int hws_pex_config(const struct serdes_map *serdes_map, u8 count);
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void board_pex_config(void);
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#endif
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