mirror of
https://github.com/AsahiLinux/u-boot
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93c7b879c7
Now that we have generic EFI payload support for all x86 boards, drop the QEMU-specific one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
195 lines
4.4 KiB
C
195 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <pci.h>
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#include <qfw.h>
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#include <asm/irq.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/arch/device.h>
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#include <asm/arch/qemu.h>
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static bool i440fx;
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#ifdef CONFIG_QFW
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/* on x86, the qfw registers are all IO ports */
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#define FW_CONTROL_PORT 0x510
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#define FW_DATA_PORT 0x511
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#define FW_DMA_PORT_LOW 0x514
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#define FW_DMA_PORT_HIGH 0x518
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static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
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uint32_t size, void *address)
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{
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uint32_t i = 0;
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uint8_t *data = address;
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/*
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* writting FW_CFG_INVALID will cause read operation to resume at
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* last offset, otherwise read will start at offset 0
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*
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* Note: on platform where the control register is IO port, the
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* endianness is little endian.
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*/
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if (entry != FW_CFG_INVALID)
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outw(cpu_to_le16(entry), FW_CONTROL_PORT);
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/* the endianness of data register is string-preserving */
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while (size--)
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data[i++] = inb(FW_DATA_PORT);
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}
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static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
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{
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/* the DMA address register is big endian */
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outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH);
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while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
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__asm__ __volatile__ ("pause");
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}
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static struct fw_cfg_arch_ops fwcfg_x86_ops = {
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.arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
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.arch_read_dma = qemu_x86_fwcfg_read_entry_dma
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};
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#endif
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static void enable_pm_piix(void)
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{
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u8 en;
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u16 cmd;
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/* Set the PM I/O base */
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pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
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/* Enable access to the PM I/O space */
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pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_IO;
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pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
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/* PM I/O Space Enable (PMIOSE) */
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pci_read_config8(PIIX_PM, PMREGMISC, &en);
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en |= PMIOSE;
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pci_write_config8(PIIX_PM, PMREGMISC, en);
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}
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static void enable_pm_ich9(void)
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{
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/* Set the PM I/O base */
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pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
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}
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static void qemu_chipset_init(void)
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{
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u16 device, xbcs;
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int pam, i;
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/*
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* i440FX and Q35 chipset have different PAM register offset, but with
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* the same bitfield layout. Here we determine the offset based on its
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* PCI device ID.
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*/
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pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
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i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
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pam = i440fx ? I440FX_PAM : Q35_PAM;
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/*
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* Initialize Programmable Attribute Map (PAM) Registers
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*
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* Configure legacy segments C/D/E/F to system RAM
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*/
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for (i = 0; i < PAM_NUM; i++)
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pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
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if (i440fx) {
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/*
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* Enable legacy IDE I/O ports decode
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*
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* Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
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* However Linux ata_piix driver does sanity check on these two
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* registers to see whether legacy ports decode is turned on.
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* This is to make Linux ata_piix driver happy.
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*/
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pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
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pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
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/* Enable I/O APIC */
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pci_read_config16(PIIX_ISA, XBCS, &xbcs);
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xbcs |= APIC_EN;
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pci_write_config16(PIIX_ISA, XBCS, xbcs);
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enable_pm_piix();
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} else {
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/* Configure PCIe ECAM base address */
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pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
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CONFIG_PCIE_ECAM_BASE | BAR_EN);
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enable_pm_ich9();
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}
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#ifdef CONFIG_QFW
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qemu_fwcfg_init(&fwcfg_x86_ops);
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#endif
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}
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#if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
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int arch_cpu_init(void)
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{
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post_code(POST_CPU_INIT);
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return x86_cpu_init_f();
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}
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int checkcpu(void)
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{
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return 0;
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}
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int print_cpuinfo(void)
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{
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post_code(POST_CPU_INFO);
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return default_print_cpuinfo();
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}
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#endif
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void reset_cpu(ulong addr)
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{
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/* cold reset */
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x86_full_reset();
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}
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int arch_early_init_r(void)
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{
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qemu_chipset_init();
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return 0;
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}
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#ifdef CONFIG_GENERATE_MP_TABLE
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int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
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{
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u8 irq;
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if (i440fx) {
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/*
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* Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
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* connected to I/O APIC INTPIN#16-19. Instead they are routed
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* to an irq number controled by the PIRQ routing register.
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*/
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pci_read_config8(PCI_BDF(bus, dev, func),
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PCI_INTERRUPT_LINE, &irq);
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} else {
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/*
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* ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
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* PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
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*/
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irq = pirq < 8 ? pirq + 16 : pirq + 12;
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}
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return irq;
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}
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#endif
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