mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
a8542ad81f
This is not used anywhere. Clean this up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
481 lines
11 KiB
C
481 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* From Coreboot file of same name
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 The Chromium Authors
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/cpu.h>
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#include <asm/cpu_x86.h>
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#include <asm/msr.h>
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#include <asm/msr-index.h>
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#include <asm/mtrr.h>
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#include <asm/processor.h>
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#include <asm/speedstep.h>
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#include <asm/turbo.h>
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#include <asm/arch/model_206ax.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void enable_vmx(void)
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{
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struct cpuid_result regs;
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#ifdef CONFIG_ENABLE_VMX
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int enable = true;
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#else
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int enable = false;
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#endif
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msr_t msr;
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regs = cpuid(1);
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/* Check that the VMX is supported before reading or writing the MSR. */
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if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX)))
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return;
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msr = msr_read(MSR_IA32_FEATURE_CONTROL);
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if (msr.lo & (1 << 0)) {
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debug("VMX is locked, so %s will do nothing\n", __func__);
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/* VMX locked. If we set it again we get an illegal
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* instruction
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*/
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return;
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}
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/* The IA32_FEATURE_CONTROL MSR may initialize with random values.
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* It must be cleared regardless of VMX config setting.
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*/
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msr.hi = 0;
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msr.lo = 0;
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debug("%s VMX\n", enable ? "Enabling" : "Disabling");
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/*
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* Even though the Intel manual says you must set the lock bit in
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* addition to the VMX bit in order for VMX to work, it is incorrect.
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* Thus we leave it unlocked for the OS to manage things itself.
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* This is good for a few reasons:
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* - No need to reflash the bios just to toggle the lock bit.
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* - The VMX bits really really should match each other across cores,
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* so hard locking it on one while another has the opposite setting
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* can easily lead to crashes as code using VMX migrates between
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* them.
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* - Vendors that want to "upsell" from a bios that disables+locks to
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* one that doesn't is sleazy.
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* By leaving this to the OS (e.g. Linux), people can do exactly what
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* they want on the fly, and do it correctly (e.g. across multiple
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* cores).
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*/
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if (enable) {
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msr.lo |= (1 << 2);
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if (regs.ecx & CPUID_SMX)
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msr.lo |= (1 << 1);
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}
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msr_write(MSR_IA32_FEATURE_CONTROL, msr);
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}
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/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
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static const u8 power_limit_time_sec_to_msr[] = {
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[0] = 0x00,
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[1] = 0x0a,
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[2] = 0x0b,
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[3] = 0x4b,
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[4] = 0x0c,
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[5] = 0x2c,
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[6] = 0x4c,
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[7] = 0x6c,
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[8] = 0x0d,
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[10] = 0x2d,
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[12] = 0x4d,
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[14] = 0x6d,
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[16] = 0x0e,
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[20] = 0x2e,
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[24] = 0x4e,
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[28] = 0x6e,
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[32] = 0x0f,
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[40] = 0x2f,
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[48] = 0x4f,
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[56] = 0x6f,
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[64] = 0x10,
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[80] = 0x30,
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[96] = 0x50,
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[112] = 0x70,
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[128] = 0x11,
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};
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/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
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static const u8 power_limit_time_msr_to_sec[] = {
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[0x00] = 0,
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[0x0a] = 1,
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[0x0b] = 2,
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[0x4b] = 3,
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[0x0c] = 4,
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[0x2c] = 5,
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[0x4c] = 6,
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[0x6c] = 7,
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[0x0d] = 8,
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[0x2d] = 10,
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[0x4d] = 12,
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[0x6d] = 14,
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[0x0e] = 16,
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[0x2e] = 20,
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[0x4e] = 24,
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[0x6e] = 28,
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[0x0f] = 32,
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[0x2f] = 40,
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[0x4f] = 48,
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[0x6f] = 56,
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[0x10] = 64,
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[0x30] = 80,
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[0x50] = 96,
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[0x70] = 112,
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[0x11] = 128,
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};
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int cpu_config_tdp_levels(void)
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{
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struct cpuid_result result;
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msr_t platform_info;
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/* Minimum CPU revision */
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result = cpuid(1);
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if (result.eax < IVB_CONFIG_TDP_MIN_CPUID)
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return 0;
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/* Bits 34:33 indicate how many levels supported */
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platform_info = msr_read(MSR_PLATFORM_INFO);
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return (platform_info.hi >> 1) & 3;
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}
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/*
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* Configure processor power limits if possible
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* This must be done AFTER set of BIOS_RESET_CPL
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*/
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void set_power_limits(u8 power_limit_1_time)
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{
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msr_t msr = msr_read(MSR_PLATFORM_INFO);
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msr_t limit;
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unsigned power_unit;
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unsigned tdp, min_power, max_power, max_time;
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u8 power_limit_1_val;
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if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
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return;
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if (!(msr.lo & PLATFORM_INFO_SET_TDP))
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return;
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/* Get units */
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msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
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power_unit = 2 << ((msr.lo & 0xf) - 1);
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/* Get power defaults for this SKU */
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msr = msr_read(MSR_PKG_POWER_SKU);
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tdp = msr.lo & 0x7fff;
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min_power = (msr.lo >> 16) & 0x7fff;
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max_power = msr.hi & 0x7fff;
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max_time = (msr.hi >> 16) & 0x7f;
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debug("CPU TDP: %u Watts\n", tdp / power_unit);
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if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
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power_limit_1_time = power_limit_time_msr_to_sec[max_time];
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if (min_power > 0 && tdp < min_power)
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tdp = min_power;
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if (max_power > 0 && tdp > max_power)
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tdp = max_power;
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power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
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/* Set long term power limit to TDP */
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limit.lo = 0;
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limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
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limit.lo |= PKG_POWER_LIMIT_EN;
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limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
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PKG_POWER_LIMIT_TIME_SHIFT;
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/* Set short term power limit to 1.25 * TDP */
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limit.hi = 0;
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limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
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limit.hi |= PKG_POWER_LIMIT_EN;
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/* Power limit 2 time is only programmable on SNB EP/EX */
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msr_write(MSR_PKG_POWER_LIMIT, limit);
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/* Use nominal TDP values for CPUs with configurable TDP */
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if (cpu_config_tdp_levels()) {
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msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
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limit.hi = 0;
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limit.lo = msr.lo & 0xff;
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msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
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}
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}
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static void configure_c_states(void)
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{
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struct cpuid_result result;
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msr_t msr;
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msr = msr_read(MSR_PMG_CST_CONFIG_CTL);
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msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
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msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
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msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
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msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
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msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
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msr.lo |= 7; /* No package C-state limit */
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msr_write(MSR_PMG_CST_CONFIG_CTL, msr);
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msr = msr_read(MSR_PMG_IO_CAPTURE_ADR);
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msr.lo &= ~0x7ffff;
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msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */
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msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */
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msr_write(MSR_PMG_IO_CAPTURE_ADR, msr);
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msr = msr_read(MSR_MISC_PWR_MGMT);
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msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
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msr_write(MSR_MISC_PWR_MGMT, msr);
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msr = msr_read(MSR_POWER_CTL);
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msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
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msr.lo |= (1 << 1); /* C1E Enable */
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msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
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msr_write(MSR_POWER_CTL, msr);
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/* C3 Interrupt Response Time Limit */
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msr.hi = 0;
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msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
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msr_write(MSR_PKGC3_IRTL, msr);
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/* C6 Interrupt Response Time Limit */
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msr.hi = 0;
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msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
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msr_write(MSR_PKGC6_IRTL, msr);
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/* C7 Interrupt Response Time Limit */
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msr.hi = 0;
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msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
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msr_write(MSR_PKGC7_IRTL, msr);
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/* Primary Plane Current Limit */
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msr = msr_read(MSR_PP0_CURRENT_CONFIG);
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msr.lo &= ~0x1fff;
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msr.lo |= PP0_CURRENT_LIMIT;
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msr_write(MSR_PP0_CURRENT_CONFIG, msr);
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/* Secondary Plane Current Limit */
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msr = msr_read(MSR_PP1_CURRENT_CONFIG);
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msr.lo &= ~0x1fff;
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result = cpuid(1);
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if (result.eax >= 0x30600)
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msr.lo |= PP1_CURRENT_LIMIT_IVB;
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else
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msr.lo |= PP1_CURRENT_LIMIT_SNB;
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msr_write(MSR_PP1_CURRENT_CONFIG, msr);
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}
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static int configure_thermal_target(struct udevice *dev)
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{
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int tcc_offset;
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msr_t msr;
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tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"tcc-offset", 0);
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/* Set TCC activaiton offset if supported */
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msr = msr_read(MSR_PLATFORM_INFO);
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if ((msr.lo & (1 << 30)) && tcc_offset) {
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msr = msr_read(MSR_TEMPERATURE_TARGET);
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msr.lo &= ~(0xf << 24); /* Bits 27:24 */
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msr.lo |= (tcc_offset & 0xf) << 24;
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msr_write(MSR_TEMPERATURE_TARGET, msr);
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}
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return 0;
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}
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static void configure_misc(void)
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{
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msr_t msr;
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msr = msr_read(IA32_MISC_ENABLE);
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msr.lo |= (1 << 0); /* Fast String enable */
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msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
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msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
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msr_write(IA32_MISC_ENABLE, msr);
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/* Disable Thermal interrupts */
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msr.lo = 0;
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msr.hi = 0;
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msr_write(IA32_THERM_INTERRUPT, msr);
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/* Enable package critical interrupt only */
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msr.lo = 1 << 4;
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msr.hi = 0;
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msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr);
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}
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static void enable_lapic_tpr(void)
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{
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msr_t msr;
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msr = msr_read(MSR_PIC_MSG_CONTROL);
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msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
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msr_write(MSR_PIC_MSG_CONTROL, msr);
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}
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static void configure_dca_cap(void)
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{
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struct cpuid_result cpuid_regs;
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msr_t msr;
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/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
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cpuid_regs = cpuid(1);
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if (cpuid_regs.ecx & (1 << 18)) {
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msr = msr_read(IA32_PLATFORM_DCA_CAP);
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msr.lo |= 1;
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msr_write(IA32_PLATFORM_DCA_CAP, msr);
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}
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}
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static void set_max_ratio(void)
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{
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msr_t msr, perf_ctl;
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perf_ctl.hi = 0;
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/* Check for configurable TDP option */
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if (cpu_config_tdp_levels()) {
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/* Set to nominal TDP ratio */
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msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
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perf_ctl.lo = (msr.lo & 0xff) << 8;
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} else {
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/* Platform Info bits 15:8 give max ratio */
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msr = msr_read(MSR_PLATFORM_INFO);
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perf_ctl.lo = msr.lo & 0xff00;
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}
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msr_write(MSR_IA32_PERF_CTL, perf_ctl);
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debug("model_x06ax: frequency set to %d\n",
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((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
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}
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static void set_energy_perf_bias(u8 policy)
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{
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msr_t msr;
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/* Energy Policy is bits 3:0 */
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msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS);
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msr.lo &= ~0xf;
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msr.lo |= policy & 0xf;
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msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr);
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debug("model_x06ax: energy policy set to %u\n", policy);
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}
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static void configure_mca(void)
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{
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msr_t msr;
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int i;
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msr.lo = 0;
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msr.hi = 0;
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/* This should only be done on a cold boot */
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for (i = 0; i < 7; i++)
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msr_write(IA32_MC0_STATUS + (i * 4), msr);
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}
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static int model_206ax_init(struct udevice *dev)
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{
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int ret;
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/* Clear out pending MCEs */
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configure_mca();
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/* Enable the local cpu apics */
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enable_lapic_tpr();
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/* Enable virtualization if enabled in CMOS */
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enable_vmx();
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/* Configure C States */
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configure_c_states();
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/* Configure Enhanced SpeedStep and Thermal Sensors */
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configure_misc();
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/* Thermal throttle activation offset */
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ret = configure_thermal_target(dev);
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if (ret) {
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debug("Cannot set thermal target\n");
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return ret;
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}
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/* Enable Direct Cache Access */
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configure_dca_cap();
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/* Set energy policy */
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set_energy_perf_bias(ENERGY_POLICY_NORMAL);
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/* Set Max Ratio */
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set_max_ratio();
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/* Enable Turbo */
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turbo_enable();
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return 0;
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}
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static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info)
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{
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msr_t msr;
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msr = msr_read(MSR_IA32_PERF_CTL);
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info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;
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info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
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1 << CPU_FEAT_UCODE;
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return 0;
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}
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static int model_206ax_get_count(struct udevice *dev)
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{
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return 4;
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}
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static int cpu_x86_model_206ax_probe(struct udevice *dev)
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{
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if (dev->seq == 0)
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model_206ax_init(dev);
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return 0;
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}
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static const struct cpu_ops cpu_x86_model_206ax_ops = {
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.get_desc = cpu_x86_get_desc,
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.get_info = model_206ax_get_info,
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.get_count = model_206ax_get_count,
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.get_vendor = cpu_x86_get_vendor,
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};
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static const struct udevice_id cpu_x86_model_206ax_ids[] = {
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{ .compatible = "intel,core-gen3" },
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{ }
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};
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U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = {
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.name = "cpu_x86_model_206ax",
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.id = UCLASS_CPU,
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.of_match = cpu_x86_model_206ax_ids,
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.bind = cpu_x86_bind,
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.probe = cpu_x86_model_206ax_probe,
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.ops = &cpu_x86_model_206ax_ops,
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};
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